A5976
Microstepping DMOS Driver with Translator
is selected. If the voltage on the PFD input is less than 0.21 ×
VDD, then fast-decay is selected. Mixed-decay is selected when
the voltage on the PFD input is between these two levels. This
terminal should be decoupled with a 0.1 µF capacitor.
RC Blanking
In addition to the fixed off-time of the PWM control circuit, the
CT component sets the comparator blanking time. This func-
tion blanks the output of the current-sense comparator when the
outputs are switched by the internal current-control circuitry. The
comparator output is blanked to prevent false overcurrent detec-
tion due to reverse-recovery currents of the clamp diodes, and/
or switching transients related to the capacitance of the load. The
blank time, tBLANK, can be approximated by:
Mixed-Decay Operation
If the voltage on the PFD input is between 0.6 × VDD and 0.21
× VDD, the bridge will operate in mixed-decay mode for con-
trol steps when the output current decay is user-selectable (see
DECAY Input section). As the trip point is reached, the bridge
will go into fast-decay mode until the voltage on the RC terminal
decays to the voltage applied to the PFD terminal. The time the
bridge remains in fast decay is approximated by:
tBLANK = 1400 × CT
Step Input (STEP)
t
FD = RT × CT × In (0.6 × VDD / VPFD)
A low-to-high transition on the STEP input sequences the transla-
tor and advances the motor one increment. The translator controls
the input to the DACs and the direction of current flow in each
winding. The size of the increment is determined by the state of
inputs MS1 and MS2 (see Table 1).
After this fast-decay portion, tFD, the bridge will switch to slow-
decay mode for the remainder of the fixed off-time period.
Reset Input (RESETn)
The RESETn input (active low) sets the translator to a predefined
home state (see figures for home state conditions) and turns off
all of the DMOS outputs. All STEP inputs are ignored until the
RESETn input goes high.
Microstep Select (MS1 and MS2)
Input terminals MS1 and MS2 select the microstepping format
per Table 1. Changes to these inputs do not take effect until the
STEP command.
Fault Output (FAULTn)
Direction Input (DIR)
The FAULTn terminal is an open-drain output which is pulled
low when an OCP condition exists. An OCP is latched until the
device is reset via the RESETn terminal or the voltage on VBB is
cycled.
The state of the DIR input will determine the direction of rotation
of the motor.
DECAY Input
Synchronous Rectification
DECAY is a logic input that determines how the decay mode is
selected when stepping the motor. If the DECAY input is high
and a step is made such that new output levels of the DACs are
higher than or equal to their levels during the previous step, then
the decay mode for that full-bridge is set to slow. If the DECAY
input is high and a step is made such that new output levels of the
DACs are lower than their levels during the previous step, then
the decay mode for that full-bridge is determined by the PFD
input (see PFD input description). If the DECAY input is low,
then the decay mode is always determined by the PFD input (see
PFD input description).
When a PWM off-cycle is triggered by an internal current con-
trol, load current will recirculate according to the decay mode
selected by the control logic. The A5976 synchronous rectifica-
tion feature will turn on the appropriate MOSFETs during the
current decay and effectively short out the body diodes with the
low RDS(ON) driver. This will reduce power dissipation signifi-
cantly and eliminate the need for external Schottky diodes for
most applications. Reversal of the current in the motor winding
is prevented when using this mode by turning off synchronous
rectification if the current in the winding decays to zero.
Percent Fast-Decay Input (PFD)
Enable Input (ENABLEn)
Slow-, fast-, or mixed-decay is selected according to the voltage
level at the PFD input, for control steps when the output current
decay is user-selectable (see DECAY Input section). If the volt-
age at the PFD input is greater than 0.6 × VDD, then slow-decay
This active-low input enables all of the DMOS outputs. When
logic-high, the outputs are disabled. Inputs to the transla-
tor (STEP, DIR, MS1, MS2) are all active independent of the
ENABLEn input state.
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
8
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
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