Datasheet > A43P1616V-95I

A43P1616V-95I

更新时间： 2022-04-25 03:53:56

品牌	Logo	应用领域
联笙电子 - AMICC		动态存储器
页数	文件大小	规格书
42页	502K
描述
1M X 16 Bit X 4 Banks Synchronous DRAM

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数据手册

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A43P1616V-95I 数据手册

A43L2616B

Pin Descriptions

Symbol

Name

Description

CLK

System Clock

Chip Select

Active on the positive going edge to sample all inputs.

Disables or Enables device operation by masking or enabling all inputs except

CLK, CKE and L(U)DQM

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one clock + tss prior to new command.

Disable input buffers for power down in standby.

CKE

Clock Enable

Row / Column addresses are multiplexed on the same pins.

Row address : RA0~RA11, Column address: CA0~CA7

Selects bank to be activated during row address latch time.

Selects band for read/write during column address latch time.

A0~A11

Address

BA0, BA1

Bank Select Address

Row Address Strobe

Latches row addresses on the positive going edge of the CLK with RAS low.

Enables row access & precharge.

RAS

CAS

Latches column addresses on the positive going edge of the CLK with CAS low.

Enables column access.

Column Address

Strobe

Write Enable

Enables write operation and Row precharge.

Makes data output Hi-Z, t SHZ after the clock and masks the output.

Blocks data input when L(U)DQM active.

Data Input/Output

Mask

L(U)DQM

DQ0-15

Data Input/Output

Data inputs/outputs are multiplexed on the same pins.

Power

Supply/Ground

VDD/VSS

Power Supply: +3.3V±0.3V/Ground

Data Output

Power/Ground

VDDQ/VSSQ

NC/RFU

Provide isolated Power/Ground to DQs for improved noise immunity.

No Connection

(December, 2009, Version 1.3)

AMIC Technology, Corp.

1 2 345 6 7...42

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