Datasheet > A43L1616V

A43L1616V

更新时间： 2022-11-29 03:15:21

品牌	Logo	应用领域
联笙电子 - AMICC		动态存储器
页数	文件大小	规格书
44页	1269K
描述
1M X 16 Bit X 2 Banks Synchronous DRAM

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数据手册

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A43L1616V 数据手册

A43L1616

Decoupling Capacitance Guide Line

Recommended decoupling capacitance added to power line at board

Parameter

Symbol

CDC1

Value

Unit

µF

Decoupling Capacitance between VDD and VSS

Decoupling Capacitance between VDDQ and VSSQ

0.1 + 0.01

CDC2

µF

Note: 1. VDD and VDDQ pins are separated each other.

All VDD pins are connected in chip. All VDDQ pins are connected in chip.

2. VSS and VSSQ pins are separated each other

All VSS pins are connected in chip. All VSSQ pins are connected in chip.

DC Electrical Characteristics

(Recommended operating condition unless otherwise noted, TA = 0ºC to +70ºC for commercial or TA = -40ºC to +85ºC for extended)

Speed

Units Note

Symbol

Parameter

Test Conditions

-6

-7

Operating Current

(One Bank Active)

Burst Length = 1

Icc1

t^RC≥ tRC(min), tCC ≥ tCC(min), IOL = 0mA

CKE ≤ VIL(max), tCC = 15ns

Icc2 P

0.3

0.5

Precharge Standby Current

in power-down mode

Icc2 PS

CKE ≤ VIL(max), tCC = ∞

CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns

Input signals are changed one time during 30ns

ICC2N

Precharge Standby Current

in non power-down mode

CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞

Input signals are stable.

ICC2NS

ICC3P

ICC3N

Active Standby current in

non power-down mode

(One Bank Active)

1.5

CKE ≤ VIL(max), tCC = 15ns

CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns

Input signals are changed one time during 30ns

Operating Current

(Burst Mode)

I^OL= 0mA, Page Burst

All bank Activated, t^CCD= tCCD (min)

ICC4

ICC5

ICC6

Refresh Current

t^RC≥ tRC (min)

CKE ≤ 0.2V

200

Self Refresh Current

Note: 1. Measured with outputs open. Addresses are changed only one time during tCC(min).

2. Refresh period is 64ms. Addresses are changed only one time during t^CC(min).

PRELIMINARY (August, 2005, Version 0.0)

AMIC Technology, Corp.

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