A43L1616
Preliminary
1M X 16 Bit X 2 Banks Synchronous DRAM
Features
Power supply
- VDD: 3.3V VDDQ : 3.3V
LVTTL compatible with multiplexed address
All inputs are sampled at the positive going edge of the
system clock
DQM for masking
Auto & self refresh
Two banks / Pulse RAS
64ms refresh period (4K cycle)
Industrial operating temperature range: -40ºC to +85ºC
for -U series.
Available in 54 Balls CSP (8mm X 8mm) and 54-pin
TSOP(II) packages
MRS cycle with address key programs
- CAS Latency (2 & 3)
- Burst Length (1,2,4,8 & full page)
- Burst Type (Sequential & Interleave)
Clock Frequency (max) : 167MHz @ CL=3 (-6)
143MHz @ CL=3 (-7)
Package is available to lead free (-F series)
All Pb-free (Lead-free) products are RoHS compliant
General Description
The A43L1616 is 33,554,432 bits synchronous high data
rate Dynamic RAM organized as 2 X 1,048,576 words by
16 bits, fabricated with AMIC’s high performance CMOS
technology. Synchronous design allows precise cycle
control with the use of system clock. I/O transactions are
possible on every clock cycle. Range of operating
frequencies, programmable latencies allows the same
device to be useful for a variety of high bandwidth, high
performance memory system applications.
Pin Configuration
54 Balls CSP (8 mm x 8 mm)
Top View
54 Ball (6X9) CSP
1
2
3
7
8
9
A
B
C
D
E
F
VSS
DQ15
DQ13
DQ11
DQ9
NC
VSSQ
VDDQ
VSSQ
VDDQ
VSS
VDDQ
VSSQ
VDDQ
VSSQ
VDD
DQ0
DQ2
DQ4
DQ6
LDQM
VDD
DQ1
DQ3
DQ5
DQ7
DQ14
DQ12
DQ10
DQ8
UDQM
CLK
CKE
CAS
BA
RAS
NC
WE
G
NC
NC
A9
CS
A10
VDD
H
J
A8
A7
A5
A6
A4
A0
A3
A1
A2
VSS
PRELIMINARY
(February, 2008, Version 0.3)
1
AMIC Technology, Corp.