A43L0632
Preliminary
512K X 32 Bit X 2 Banks Synchronous DRAM
Features
ꢀPower supply
- VDD: 3.3V VDDQ : 3.3V
ꢀLVTTL compatible with multiplexed address
ꢀAll inputs are sampled at the positive going edge of the
system clock
ꢀDQM for masking
ꢀAuto & self refresh
ꢀTwo banks / Pulse RAS
ꢀ64ms refresh period (4K cycle)
ꢀIndustrial operating temperature range: -40ºC to +85ºC
for -U series.
ꢀAvailable in 90 Balls CSP (8mm X 13mm)
ꢀPackage is available to lead free (-F series)
ꢀMRS cycle with address key programs
- CAS Latency (2 & 3)
- Burst Length (1,2,4,8 & full page)
- Burst Type (Sequential & Interleave)
ꢀClock Frequency (max) : 167MHz @ CL=3 (-6)
143MHz @ CL=3 (-7)
General Description
The A43L0632 is 33,554,432 bits synchronous high data
rate Dynamic RAM organized as 2 X 524,288 words by 32
bits, fabricated with AMIC’s high performance CMOS
technology. Synchronous design allows precise cycle
control with the use of system clock. I/O transactions are
possible on every clock cycle. Range of operating
frequencies, programmable latencies allows the same
device to be useful for a variety of high bandwidth, high
performance memory system applications.
Pin Configuration
ꢀ90 Balls CSP (8 mm x 13 mm)
Top View
90 Ball (8X13) CSP
1
2
3
7
8
9
A
B
C
D
E
F
DQ26
DQ28
VSSQ
VSSQ
VDDQ
VSS
A4
DQ24
VDDQ
DQ27
DQ29
DQ31
DQM3
A5
VSS
VSSQ
DQ25
DQ30
NC
VDD
VDDQ
DQ22
DQ17
NC
DQ23
VSSQ
DQ20
DQ18
DQ16
DQM2
A0
DQ21
DQ19
VDDQ
VDDQ
VSSQ
VDD
A2
A3
A1
G
H
J
A6
A10
NC
BA
A7
A8
NC
NC
NC
CLK
CKE
A9
CS
RAS
K
DQM1
NC
NC
DQM0
CAS
VDD
DQ6
WE
DQ7
DQ5
DQ3
VSSQ
DQ0
L
VDDQ
VSSQ
VSSQ
DQ11
DQ8
DQ10
DQ12
VDDQ
DQ15
VSS
DQ9
VSSQ
VDDQ
VDDQ
DQ4
M
N
P
R
DQ14
VSSQ
VSS
DQ1
VDDQ
VDD
DQ13
DQ2
PRELIMINARY
(August, 2005, Version 0.0)
1
AMIC Technology, Corp.