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A43E26161V-95U PDF预览

A43E26161V-95U

更新时间: 2024-01-28 07:04:41
品牌 Logo 应用领域
联笙电子 - AMICC 存储内存集成电路光电二极管动态存储器时钟
页数 文件大小 规格书
44页 1119K
描述
1M X 16 BIT X 4 BANKS LOW POWER SYNCHRONOUS DRAM

A43E26161V-95U 技术参数

是否Rohs认证: 符合生命周期:Contact Manufacturer
包装说明:TSOP2, TSOP54,.46,32Reach Compliance Code:unknown
风险等级:5.45Is Samacsys:N
访问模式:FOUR BANK PAGE BURST最长访问时间:7 ns
其他特性:AUTO/SELF REFRESH最大时钟频率 (fCLK):105 MHz
I/O 类型:COMMON交错的突发长度:1,2,4,8
JESD-30 代码:R-PDSO-G54长度:22.22 mm
内存密度:67108864 bit内存集成电路类型:SYNCHRONOUS DRAM
内存宽度:16功能数量:1
端口数量:1端子数量:54
字数:4194304 words字数代码:4000000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:4MX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSOP2封装等效代码:TSOP54,.46,32
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
电源:1.8 V认证状态:Not Qualified
刷新周期:4096座面最大高度:1.2 mm
自我刷新:YES连续突发长度:1,2,4,8,FP
最大待机电流:0.0003 A子类别:DRAMs
最大压摆率:0.05 mA最大供电电压 (Vsup):2 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.8 mm端子位置:DUAL
宽度:10.16 mmBase Number Matches:1

A43E26161V-95U 数据手册

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A43E26161  
1M X 16 Bit X 4 Banks Low Power Synchronous DRAM  
Features  
Low power supply  
Auto & self refresh  
- VDD: 1.8V VDDQ : 1.8V  
64ms refresh period (4K cycle)  
LVCMOS compatible with multiplexed address  
Self refresh with programmable refresh period through  
EMRS cycle  
Programmable Power Reduction Feature by partial  
array activation during Self-refresh through EMRS  
cycle  
Industrial operating temperature range: -25ºC to +85ºC  
for -U series.  
Available in 54 Balls CSP (8mm X 8mm) and 54-pin  
TSOP(II) packages.  
Four banks / Pulse RAS  
MRS cycle with address key programs  
- CAS Latency (2 & 3)  
- Burst Length (1,2,4,8 & full page)  
- Burst Type (Sequential & Interleave)  
All inputs are sampled at the positive going edge of the  
system clock  
Deep Power Down Mode  
DQM for masking  
Clock Frequency (max) : 105MHz @ CL=3 (-95)  
General Description  
The A43E26161 is 67,108,864 bits Low Power  
synchronous high data rate Dynamic RAM organized as 4  
X 1,048,576 words by 16 bits, fabricated with AMIC’s high  
performance CMOS technology. Synchronous design  
allows precise cycle control with the use of system clock.  
I/O transactions are possible on every clock cycle. Range  
of operating frequencies, programmable latencies allows  
the same device to be useful for a variety of high  
bandwidth,  
high  
performance  
memory  
system  
applications.  
Pin Configuration  
54 Balls CSP (8 mm x 8 mm)  
Top View  
54 Ball (8X8) CSP  
1
2
3
7
8
9
A
B
C
D
E
F
VSS  
DQ15  
DQ13  
DQ11  
DQ9  
NC  
VSSQ  
VDDQ  
VSSQ  
VDDQ  
VSS  
VDDQ  
VSSQ  
VDDQ  
VSSQ  
VDD  
DQ0  
DQ2  
VDD  
DQ1  
DQ3  
DQ5  
DQ7  
DQ14  
DQ12  
DQ10  
DQ8  
DQ4  
DQ6  
LDQM  
UDQM  
CLK  
CKE  
CAS  
BA0  
RAS  
BA1  
WE  
G
NC  
A11  
A9  
CS  
A10  
VDD  
H
J
A8  
A7  
A5  
A6  
A4  
A0  
A3  
A1  
A2  
VSS  
(December, 2004, Version 1.0)  
1
AMIC Technology, Corp.  

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