Datasheet > 存储 > DRAM> A43E06161V-95U

A43E06161V-95U

更新时间： 2024-01-22 06:21:44

品牌	Logo	应用领域
联笙电子 - AMICC		动态存储器
页数	文件大小	规格书
46页	1290K
描述
512K X 16 Bit X 2 Banks Synchronous DRAM

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技术参数
数据手册

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A43E06161V-95U 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.84
Is Samacsys：	N	Base Number Matches：	1

A43E06161V-95U 数据手册

A43E06161

Preliminary

512K X 16 Bit X 2 Banks Synchronous DRAM

Features

ꢀLow power supply

ꢀIndustrial operating temperature range: -40ºC to +85ºC

for –U

- VDD: 1.8V

- VDDQ: 1.8V

ꢀPb-Free type for -F

ꢀLVCMOS compatible with multiplexed address

ꢀBurst Read Single-bit Write operation

ꢀDQM for masking

ꢀAuto & self refresh

ꢀ32ms refresh period (2K cycle)

ꢀAvailable in 50-pin TSOP(II) package

ꢀDual banks / Pulse RAS

ꢀMRS cycle with address key programs

- CAS Latency (2,3)

- Burst Length (1,2,4,8 & full page)

- Burst Type (Sequential & Interleave)

ꢀAll inputs are sampled at the positive going edge of the

system clock

ꢀDeep Power Down Mode

ꢀClock Frequency: 105MHz @ CL=3 (-95)

133MHz @ CL=3 (-75)

General Description

The A43E06161 is 16,777,216 bits synchronous high data

rate Dynamic RAM organized as 2 X 524,288 words by 16

bits, fabricated with AMIC’s high performance CMOS

technology. Synchronous design allows precise cycle control

with the use of system clock. I/O transactions are possible on

every clock cycle. Range of operating frequencies,

programmable latencies allows the same device to be useful

for a variety of high bandwidth, high performance memory

system applications.

Pin Configuration

ꢀTSOP (II)

50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26

A43E06161V

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

PRELIMINARY (July, 2005, Version 0.1)

AMIC Technology, Corp.

123 4 5 6 7...46

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