Datasheet > 存储 > DRAM> A43E06161V-95U

A43E06161V-95U

更新时间： 2024-01-28 12:42:57

品牌	Logo	应用领域
联笙电子 - AMICC		动态存储器
页数	文件大小	规格书
46页	1290K
描述
512K X 16 Bit X 2 Banks Synchronous DRAM

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

A43E06161V-95U 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.84
Is Samacsys：	N	Base Number Matches：	1

A43E06161V-95U 数据手册

A43E06161

Decoupling Capacitance Guide Line

Recommended decoupling capacitance added to power line at board.

Parameter

Symbol

Value

Unit

µF

Decoupling Capacitance between VDD and VSS

Decoupling Capacitance between VDDQ and VSSQ

CDC1

CDC2

0.1 + 0.01

µF

Note: 1. VDD and VDDQ pins are separated each other.

All VDD pins are connected in chip. All VDDQ pins are connected in chip.

2. VSS and VSSQ pins are separated each other

All VSS pins are connected in chip. All VSSQ pins are connected in chip.

DC Electrical Characteristics

(Recommended operating condition unless otherwise noted, TA = 0 to 70°C or -40ºC to +85ºC)

Speed

CAS

Symbol

Parameter

Test Conditions

Unit Notes

Latency

-75

-95

Operating Current

(One Bank Active)

Burst Length = 1

Icc1

t^RC≥ tRC(min), tCC ≥ tCC(min), IOL = 0mA

Icc2 P

Precharge Standby

Current in power-

down mode

CKE ≤ VIL(max), tCC = 15ns

0.3

0.1

Icc2 PS

CKL ≤ VIL(max), tCC = ∞

CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns

ICC2N

Precharge Standby

Current in non

power-down mode

Input signals are changed one time during 30ns

CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞

Input signals are stable.

ICC2NS

ICC3 P

Active Standby

Current in power-

down mode

CKE ≤ VIL(max), tCC = 15ns

Active Standby

current in non

power-down mode

(One Bank Active)

CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns

Input signals are changed one time during 30ns

ICC3N

ICC4

Operating Current

(Burst Mode)

I^OL= 0mA, Page Burst

All bank Activated, t^CCD= tCCD (min)

ICC5

ICC6

Refresh Current

t^RC≥ tRC (min)

CKE ≤ 0.2V

Self Refresh

Current

200

µA

Deep Power Down

Current

ICC7

CKE ≤ 0.2V

µA

Note: 1. Measured with outputs open. Addresses are changed only one time during tCC(min).

2. Refresh period is 32ms. Addresses are changed only one time during t^CC(min).

PRELIMINARY (July, 2005, Version 0.1)

AMIC Technology, Corp.

1...3 4 567 8 9...46

下载PDF

与A43E06161V-95U相关器件

型号	品牌	描述	获取价格	数据表
A43E06161V-95UF	AMICC	512K X 16 Bit X 2 Banks Synchronous DRAM	获取价格
A43E0616G-75I	AMICC	1M X 16 Bit X 4 Banks Synchronous DRAM	获取价格
A43E0616G-95I	AMICC	1M X 16 Bit X 4 Banks Synchronous DRAM	获取价格
A43E0616V-75I	AMICC	1M X 16 Bit X 4 Banks Synchronous DRAM	获取价格
A43E0616V-7I	AMICC	1M X 16 Bit X 4 Banks Synchronous DRAM	获取价格
A43E0616V-95I	AMICC	1M X 16 Bit X 4 Banks Synchronous DRAM	获取价格