Datasheet > 存储 > DRAM> A42U2604V-80U

A42U2604V-80U

更新时间： 2024-01-22 08:20:55

品牌	Logo	应用领域
联笙电子 - AMICC		/
页数	文件大小	规格书
25页	267K
描述
4M X 4 CMOS DYNAMIC RAM WITH EDO PAGE MODE

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A42U2604V-80U 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	TSOP2, TSOP24/26,.36	Reach Compliance Code：	unknown
风险等级：	5.92	访问模式：	FAST PAGE
最长访问时间：	80 ns	其他特性：	RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH/SELF REFRESH
I/O 类型：	COMMON	JESD-30 代码：	R-PDSO-G24
JESD-609代码：	e0	长度：	17.14 mm
内存密度：	16777216 bit	内存集成电路类型：	EDO DRAM
内存宽度：	4	功能数量：	1
端口数量：	1	端子数量：	24
字数：	4194304 words	字数代码：	4000000
工作模式：	ASYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	4MX4
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSOP2	封装等效代码：	TSOP24/26,.36
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE
电源：	2.5 V	认证状态：	Not Qualified
刷新周期：	2048	座面最大高度：	1.2 mm
自我刷新：	YES	最大待机电流：	0.0005 A
子类别：	DRAMs	最大压摆率：	0.06 mA
最大供电电压 (Vsup)：	2.75 V	最小供电电压 (Vsup)：	2.25 V
标称供电电压 (Vsup)：	2.5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
宽度：	7.62 mm

A42U2604V-80U 数据手册

A42U2604 Series

Selection Guide

Symbol

Description

-50

-60

-80

Unit

tRAC

Maximum RAS Access Time

tAA

Maximum Column Address Access Time

tCAC

Maximum CAS Access Time

tOEA

Maximum Output Enable ( OE) Access Time

Minimum Read or Write Cycle Time

Minimum EDO Cycle Time

tRC

tPC

100

132

Functional Description

The A42U2604 reads and writes data by multiplexing an

22-bit address into a 11-bit(2K) row and column address.

valid as long as RAS and OE are low, and WE is high;

this is the only characteristic which differentiates Extended

Data Out operation from a standard Read or Fast Page

Read.

and

are used to strobe the row address and the

CAS

RAS

column address, respectively.

A Read cycle is performed by holding the WE signal high

A memory cycle is terminated by returning both RAS and

high. Memory cell data will retain its correct state by

CAS

during RAS /

operation. A Write cycle is executed by

CAS

maintaining power and accessing all 2048(2K)

combinations of the 11-bit(2K) row addresses, regardless

holding the WE signal low during RAS /

operation;

CAS

the input data is latched by the falling edge of WE or

, whichever occurs later. The data inputs and outputs

of sequence, at least once every 32ms through any RAS

CAS

are routed through 4 common I/O pins, with RAS ,

cycle (Read, Write) or RAS Refresh cycle ( RAS -only,

CBR, or Hidden). The CBR Refresh cycle automatically

controls the row addresses by invoking the refresh counter

and controller.

CAS

WE and OE controlling the in direction.

EDO Page Mode operation all 2048(2K) columns within a

selected row to be randomly accessed at a high data rate.

A EDO Page Mode cycle is initiated with a row address

Power-On

The initial application of the VCC supply requires a 200 µs

wait followed by a minimum of any eight initialization cycles

latched by RAS followed by a column address latched by

. While holding RAS low,

can be toggled to

CAS

containing a RAS clock. During Power-On, the VCC

strobe changing column addresses, thus achieving shorter

cycle times.

current is dependent on the input levels of RAS and

CAS

The A42U2604 offers an accelerated Fast Page Mode

cycle through a feature called Extended Data Out, which

It is recommended that RAS and

be held at a valid VIH during Power-On to avoid current

surges.

track with VCC or

CAS

keeps the output drivers on during the

precharge

CAS

time (tcp). Since data can be output after

goes high,

CAS

the user is not required to wait for valid data to appear

before starting the next access cycle. Data-out will remain

PRELIMINARY

(June, 2002, Version 0.3)

AMIC Technology, Inc.

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