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A42L0616V-50F PDF预览

A42L0616V-50F

更新时间: 2024-01-12 08:54:35
品牌 Logo 应用领域
联笙电子 - AMICC /
页数 文件大小 规格书
25页 273K
描述
EDO DRAM, 1MX16, 50ns, CMOS, PDSO44, TSOP2-50/44

A42L0616V-50F 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:TSOP2-50/44Reach Compliance Code:unknown
风险等级:5.84访问模式:FAST PAGE
最长访问时间:50 ns其他特性:RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH/SELF REFRESH
I/O 类型:COMMONJESD-30 代码:R-PDSO-G44
长度:20.95 mm内存密度:16777216 bit
内存集成电路类型:EDO DRAM内存宽度:16
功能数量:1端口数量:1
端子数量:44字数:1048576 words
字数代码:1000000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:1MX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSOP2
封装等效代码:TSOP44/50,.46,32封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE电源:3.3 V
认证状态:Not Qualified刷新周期:1024
座面最大高度:1.2 mm自我刷新:YES
最大待机电流:0.001 A子类别:DRAMs
最大压摆率:0.105 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:GULL WING
端子节距:0.8 mm端子位置:DUAL
宽度:10.16 mmBase Number Matches:1

A42L0616V-50F 数据手册

 浏览型号A42L0616V-50F的Datasheet PDF文件第2页浏览型号A42L0616V-50F的Datasheet PDF文件第3页浏览型号A42L0616V-50F的Datasheet PDF文件第4页浏览型号A42L0616V-50F的Datasheet PDF文件第6页浏览型号A42L0616V-50F的Datasheet PDF文件第7页浏览型号A42L0616V-50F的Datasheet PDF文件第8页 
A42L0616 Series  
Truth Table  
Function  
Address  
X
I/Os  
Notes  
RAS  
H
WE  
X
OE  
X
LCAS  
UCAS  
Standby  
H
L
H
L
L
High-Z  
Read: Word  
Read: Lower Byte  
L
H
L
Row/Col.  
Row/Col.  
Data Out  
L
H
H
L
I/O0-7 = Data Out  
I/O8-15 = High-Z  
Read: Upper Byte  
L
L
H
H
L
Row/Col.  
I/O0-7 = High-Z  
I/O8-15 = Data Out  
Write: Word  
L
L
L
L
L
L
L
H
H
Row/Col.  
Row/Col.  
Data In  
Write: Lower Byte  
H
I/O0-7 = Data In  
I/O8-15 = X  
Write: Upper Byte  
Read-Write  
L
L
L
L
H
L
L
H
Row/Col.  
Row/Col.  
I/O0-7 = X  
I/O8-15 = Data In  
1,2  
H® L  
L® H  
Data Out ® Data In  
EDO-Page-Mode Read: Hi-Z  
-First cycle  
L
L
H
H
Row/Col.  
Col.  
Data Out  
Data Out  
2
2
H® L  
H® L  
H® L  
H® L  
H® L  
H® L  
-Subsequent Cycles  
EDO-Page-Mode Write  
-First cycle  
L
L
L
L
H
H
Row/Col.  
Col.  
Data In  
Data In  
1
1
H® L  
H® L  
H® L  
H® L  
-Subsequent Cycles  
EDO-Page-Mode Read-Write  
-First cycle  
L
L
Row/Col.  
Col.  
1, 2  
1, 2  
H® L  
H® L  
L
H® L  
H® L  
L
H® L  
H® L  
H
L® H  
L® H  
L
Data Out ® Data In  
Data Out ® Data In  
Data Out  
-Subsequent Cycles  
Hidden Refresh Read  
Hidden Refresh Write  
Row/Col.  
Row/Col.  
Row  
2
1
L® H® L  
L® H® L  
L
L
L
L
X
Data In ® High-Z  
H
H
X
X
High-Z  
RAS-Only Refresh  
CBR Refresh  
L
L
L
L
X
H
X
X
X
X
High-Z  
High-Z  
3
H® L  
H® L  
Self Refresh  
Note:  
1. Byte Write may be executed with either  
2. Byte Read may be executed with either  
or  
active.  
active.  
UCAS  
LCAS  
or  
UCAS LCAS  
3. Only one  
signal (  
or  
UCAS LCAS  
) must be active.  
CAS  
PRELIMINARY  
(June, 2002, Version 0.2)  
4
AMIC Technology, Inc.  

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