Datasheet > 存储 > DRAM> A42L0616V-50F

A42L0616V-50F

更新时间： 2024-01-14 03:34:29

品牌	Logo	应用领域
联笙电子 - AMICC		/
页数	文件大小	规格书
25页	273K
描述
EDO DRAM, 1MX16, 50ns, CMOS, PDSO44, TSOP2-50/44

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技术参数
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A42L0616V-50F 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
包装说明：	TSOP2-50/44	Reach Compliance Code：	unknown
风险等级：	5.84	访问模式：	FAST PAGE
最长访问时间：	50 ns	其他特性：	RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH/SELF REFRESH
I/O 类型：	COMMON	JESD-30 代码：	R-PDSO-G44
长度：	20.95 mm	内存密度：	16777216 bit
内存集成电路类型：	EDO DRAM	内存宽度：	16
功能数量：	1	端口数量：	1
端子数量：	44	字数：	1048576 words
字数代码：	1000000	工作模式：	ASYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	1MX16	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	TSOP2
封装等效代码：	TSOP44/50,.46,32	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE	电源：	3.3 V
认证状态：	Not Qualified	刷新周期：	1024
座面最大高度：	1.2 mm	自我刷新：	YES
最大待机电流：	0.001 A	子类别：	DRAMs
最大压摆率：	0.105 mA	最大供电电压 (Vsup)：	3.6 V
最小供电电压 (Vsup)：	3 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子节距：	0.8 mm	端子位置：	DUAL
宽度：	10.16 mm	Base Number Matches：	1

A42L0616V-50F 数据手册

A42L0616 Series

Selection Guide

Symbol

Description

-45

-50

Unit

tRAC

Maximum RAS Access Time

tAA

Maximum Column Address Access Time

Maximum CAS Access Time

tCAC

tOEA

Maximum Output Enable ( OE) Access Time

Minimum Read or Write Cycle Time

Minimum EDO Cycle Time

tRC

tPC

Functional Description

The A42L0616 reads and writes data by multiplexing an

20-bit address into a 10-bit row and 10-bit column address.

The A42L0616 offers an accelerated Fast Page Mode

cycle through a feature called Extended Data Out, which

and

are used to strobe the row address and the

keeps the output drivers on during the

precharge

RAS

CAS

column address, respectively.

time (tcp). Since data can be output after

goes high,

CAS

the user is not required to wait for valid data to appear

before starting the next access cycle. Data-out will remain

The A42L0616 has two

CAS

inputs:

controls I/O0-

LCAS

valid as long as RAS and OE are low, and WE is high;

this is the only characteristic which differentiates Extended

Data Out operation from a standard Read or Fast Page

Read.

I/O7, and

controls I/O8 - I/O15,

and

UCAS

LCAS

function in an identical manner to

in that either will

CAS

generate an internal

signal. The

function and

CAS

timing are determined by the first

(

UCAS

A memory cycle is terminated by returning both RAS and

) to transition low and by the last to transition high.

LCAS

high. Memory cell data will retain its correct state by

maintaining power and accessing all 1024(1K)

combinations of the 10-bit row addresses, regardless of

CAS

Byte Read and Byte Write are controlled by using

LCAS

and

separately.

UCAS

sequence, at least once every 16ms through any RAS

A Read cycle is performed by holding the WE signal high

during RAS/ operation. A Write cycle is executed by

cycle (Read, Write) or RAS Refresh cycle ( RAS -only,

CBR, or Hidden). The CBR Refresh cycle automatically

controls the row addresses by invoking the refresh counter

and controller.

CAS

holding the WE signal low during RAS /

operation;

CAS

the input data is latched by the falling edge of WE or

, whichever occurs later. The data inputs and outputs

CAS

are routed through 16 common I/O pins, with RAS,

Power-On

CAS

The initial application of the VCC supply requires a 200 µs

wait followed by a minimum of any eight initialization cycles

WE and OE controlling the in direction.

EDO Page Mode operation all 1024(1K) columns within a

selected row to be randomly accessed at a high data rate.

A EDO Page Mode cycle is initiated with a row address

containing a RAS clock. During Power-On, the VCC

current is dependent on the input levels of RAS and

CAS

It is recommended that RAS and

track with VCC or

CAS

latched by RAS followed by a column address latched by

be held at a valid VIH during Power-On to avoid current

surges.

. While holding RAS low,

can be toggled to

CAS

strobe changing column addresses, thus achieving shorter

cycle times.

PRELIMINARY

(June, 2002, Version 0.2)

AMIC Technology, Inc.

1 234 5 6 7...25

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