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A416316BS-40 PDF预览

A416316BS-40

更新时间: 2024-02-08 20:54:50
品牌 Logo 应用领域
联笙电子 - AMICC /
页数 文件大小 规格书
25页 405K
描述
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE

A416316BS-40 技术参数

是否Rohs认证:符合生命周期:Obsolete
包装说明:SOJ, SOJ40,.44Reach Compliance Code:unknown
风险等级:5.84Is Samacsys:N
最长访问时间:40 nsI/O 类型:COMMON
JESD-30 代码:R-PDSO-J40内存密度:1048576 bit
内存集成电路类型:FAST PAGE DRAM内存宽度:16
端子数量:40字数:65536 words
字数代码:64000最高工作温度:70 °C
最低工作温度:组织:64KX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:SOJ封装等效代码:SOJ40,.44
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
电源:5 V认证状态:Not Qualified
刷新周期:256自我刷新:YES
最大待机电流:0.002 A子类别:DRAMs
最大压摆率:0.075 mA标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:J BEND
端子节距:1.27 mm端子位置:DUAL
Base Number Matches:1

A416316BS-40 数据手册

 浏览型号A416316BS-40的Datasheet PDF文件第1页浏览型号A416316BS-40的Datasheet PDF文件第3页浏览型号A416316BS-40的Datasheet PDF文件第4页浏览型号A416316BS-40的Datasheet PDF文件第5页浏览型号A416316BS-40的Datasheet PDF文件第6页浏览型号A416316BS-40的Datasheet PDF文件第7页 
A416316B Series  
Preliminary  
64K X 16 CMOS DYNAMIC RAM WITH FAST PAGE MODE  
Features  
nSeparate CAS (  
nSelf refresh mode  
n256 refresh cycles, 4 ms refresh interval  
,
) for byte selection  
LCAS  
UCAS  
nOrganization: 65,536 words X 16 bits  
nPart Identification:  
- A416316B  
- A416316B-L (with self-refresh mode)  
nHigh speed  
nRead-modify-write, RAS -only, CAS -before- RAS ,  
Hidden refresh capability  
nTTL-compatible, three-state I/O  
nJEDEC standard packages  
- 30/35/40 ns RAS access time  
- 16/18/20 ns column address access time  
- 400mil, 40-pin SOJ  
- 10/11/12 ns CAS access time  
nLow power consumption  
- Operating: 75mA (-30 max)  
- Standby: 3 mA (TTL)  
- 400mil, 40/44 TSOP type II package  
n Single 5V power supply/built-in VBB generator  
Pin Configuration  
Pin Descriptions  
n SOJ  
nTSOP  
Symbol  
Description  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
VSS  
I/O15  
I/O14  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
VSS  
I/O15  
I/O14  
I/O13  
I/O12  
VSS  
I/O11  
I/O10  
I/O9  
VCC  
VCC  
I/O0  
I/O1  
I/O2  
I/O3  
VCC  
I/O4  
I/O5  
I/O6  
I/O7  
1
1
2
2
I/O0  
I/O1  
I/O2  
I/O3  
VCC  
I/O4  
I/O5  
I/O6  
I/O7  
NC  
A0 – A7  
Address Inputs  
3
3
4
I/O13  
I/O12  
VSS  
I/O11  
I/O10  
I/O9  
I/O8  
NC  
4
I/O0 - I/O15 Data Input/Output  
5
5
6
6
Row Address Strobe  
RAS  
7
7
8
8
9
9
Column Address Strobe/Upper Byte Control  
UCAS  
LCAS  
WE  
I/O8  
10  
11  
12  
13  
14  
15  
10  
32  
31  
30  
29  
28  
27  
26  
25  
NC  
LCAS  
UCAS  
OE  
NC  
NC  
NC  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
Column Address Strobe/Lower Byte Control  
Write Enable  
LCAS  
WE  
RAS  
NC  
A0  
A1  
A2  
UCAS  
OE  
WE  
RAS  
NC  
A0  
A1  
A2  
NC  
NC  
A7  
A6  
A5  
A7  
16  
17  
18  
19  
20  
A6  
Output Enable  
OE  
A5  
A4  
VSS  
22  
21  
A3  
VCC  
24  
23  
A4  
VSS  
VCC  
VSS  
NC  
+5V Power Supply  
Ground  
A3  
VCC  
No Connection  
PRELIMINARY (November, 2000, Version 0.0)  
1
AMIC Technology, Inc.  

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