A3983SLPTR

更新时间： 2024-02-13 22:28:12

品牌	Logo	应用领域
急速微 - ALLEGRO		驱动器运动控制电子器件信号电路光电二极管电动机控制
页数	文件大小	规格书
13页	342K
描述
DMOS Microstepping Driver with Translator

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技术参数
数据手册

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A3983SLPTR 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	TSSOP
包装说明：	HTSSOP, TSSOP24,.25	针数：	24
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	1.67
Is Samacsys：	N	其他特性：	ALSO REQUIRES A 8V TO 35V SUPPLY
模拟集成电路 - 其他类型：	STEPPER MOTOR CONTROLLER	JESD-30 代码：	R-PDSO-G24
JESD-609代码：	e3	长度：	7.8 mm
湿度敏感等级：	2	功能数量：	1
端子数量：	24	最高工作温度：	85 °C
最低工作温度：	-20 °C	最大输出电流：	2 A
封装主体材料：	PLASTIC/EPOXY	封装代码：	HTSSOP
封装等效代码：	TSSOP24,.25	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, HEAT SINK/SLUG, THIN PROFILE, SHRINK PITCH	峰值回流温度（摄氏度）：	260
电源：	3.3/5,35 V	认证状态：	Not Qualified
座面最大高度：	1.2 mm	子类别：	Motion Control Electronics
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	3 V
表面贴装：	YES	技术：	NMOS
温度等级：	OTHER	端子面层：	Matte Tin (Sn)
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	40
宽度：	4.4 mm	Base Number Matches：	1

A3983SLPTR 数据手册

A3983

DMOS Microstepping Driver with Translator

pin is tied to an external voltage > 3 V, then t_OFFdefaults to

30 μs. The ROSC pin can be safely connected to the VDD

pin for this purpose. The value of t_OFF(μs) is approximately

Shutdown. In the event of a fault, overtemperature

(excess T_J) or an undervoltage (on VCP), the DMOS out-

puts of the A3983 are disabled until the fault condition is

removed. At power-on, the UVLO (undervoltage lockout)

circuit disables the DMOS outputs and resets the translator to

the Home state.

t_OFF≈ R_OSC⁄ 825

Blanking. This function blanks the output of the current

sense comparators when the outputs are switched by the

internal current control circuitry. The comparator outputs are

blanked to prevent false overcurrent detection due to reverse

recovery currents of the clamp diodes, and switching tran-

sients related to the capacitance of the load. The blank time,

t_BLANK(μs), is approximately

Sleep Mode (SLEEP). To minimize power consumption

when the motor is not in use, this input disables much of the

internal circuitry including the output DMOS FETs, current

regulator, and charge pump. A logic low on the SLEEP pin

puts the A3983 into Sleep mode. A logic high allows normal

operation, as well as start-up (at which time the A3983 drives

the motor to the Home microstep position). When emerging

from Sleep mode, in order to allow the charge pump to stabi-

lize, provide a delay of 1 ms before issuing a Step command.

t_BLANK≈ 1 μs

Charge Pump (CP1 and CP2). The charge pump is

used to generate a gate supply greater than that of VBB

for driving the source-side DMOS gates. A 0.1 μF ceramic

capacitor, should be connected between CP1 and CP2. In

addition, a 0.1 μF ceramic capacitor is required between

VCP and VBB, to act as a reservoir for operating the

high-side DMOS gates.

Mixed Decay Operation. The bridge can operate in

Mixed Decay mode, depending on the step sequence, as

shown in figures 3 thru 5. As the trip point is reached, the

A3983 initially goes into a fast decay mode for 31.25% of

the off-time. t_OFF. After that, it switches to Slow Decay mode

for the remainder of t_OFF

VREG (VREG). This internally-generated voltage is used

to operate the sink-side DMOS outputs. The VREG pin must

be decoupled with a 0.22 μF ceramic capacitor to ground.

VREG is internally monitored. In the case of a fault condi-

tion, the DMOS outputs of the A3983 are disabled.

Synchronous Rectification. When a PWM-off cycle

is triggered by an internal fixed–off-time cycle, load current

recirculates according to the decay mode selected by the

control logic. This synchronous rectification feature turns on

the appropriate FETs during current decay, and effectively

shorts out the body diodes with the low DMOS R_DS(ON). This

reduces power dissipation significantly, and can eliminate

the need for external Schottky diodes in many applications.

Turning off synchronous rectification prevents the reversal of

the load current when a zero-current level is detected.

Enable Input (ENABLE). This input turns on or off all of

the DMOS outputs. When set to a logic high, the outputs are

disabled. When set to a logic low, the internal control enables

the outputs as required. The translator inputs STEP, DIR,

MS1, and MS2, as well as the internal sequencing logic, all

remain active, independent of the ENABLE input state.

Allegro MicroSystems, LLC

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

1...3 4 567 8 9...13

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与A3983SLPTR相关器件

型号	品牌	描述	获取价格	数据表
A3983SLPTR-T	ALLEGRO	DMOS Microstepping Driver with Translator	获取价格
A3984	ALLEGRO	DMOS Microstepping Driver with Translator	获取价格
A3984_08	ALLEGRO	The A3984 is a complete microstepping motor driver with built-in translator for easy opera	获取价格
A3984_13	ALLEGRO	DMOS Microstepping Driver with Translator	获取价格
A3984SLP	ALLEGRO	DMOS Microstepping Driver with Translator	获取价格
A3984SLP-T	ALLEGRO	DMOS Microstepping Driver with Translator	获取价格

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