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A3959SB PDF预览

A3959SB

更新时间: 2024-02-06 13:34:18
品牌 Logo 应用领域
急速微 - ALLEGRO 驱动器运动控制电子器件信号电路光电二极管电动机控制电机
页数 文件大小 规格书
12页 275K
描述
DMOS FULL-BRIDGE PWM MOTOR DRIVER

A3959SB 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:TSSOP
包装说明:HTSSOP, TSSOP28,.25针数:28
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:1.06
模拟集成电路 - 其他类型:STEPPER MOTOR CONTROLLERJESD-30 代码:R-PDSO-G28
JESD-609代码:e3长度:9.7 mm
湿度敏感等级:2功能数量:1
端子数量:28最高工作温度:85 °C
最低工作温度:-20 °C最大输出电流:6 A
封装主体材料:PLASTIC/EPOXY封装代码:HTSSOP
封装等效代码:TSSOP28,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, HEAT SINK/SLUG, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):260
电源:5 V认证状态:Not Qualified
座面最大高度:1.2 mm子类别:Motion Control Electronics
最大供电电流 (Isup):10 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:NMOS
温度等级:OTHER端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:4.4 mmBase Number Matches:1

A3959SB 数据手册

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3959  
DMOS FULL-BRIDGE  
PWM MOTOR DRIVER  
FUNCTIONAL DESCRIPTION  
EXT MODE Logic. When using external PWM current  
control, the EXT MODE input determines the current path  
during the chopped cycle. With EXT MODE low, fast  
decay mode, the opposite pair of selected outputs will be  
enabled during the off cycle. With EXT MODE high,  
slow decay mode, both sink drivers are on with ENABLE  
low.  
VREG. This internally generated voltage is used to operate  
the sink-side DMOS outputs. The VREG terminal should  
be decoupled with a 0.22 µF capacitor to ground. VREG is  
internally monitored and in the case of a fault condition,  
the outputs of the device are disabled.  
Charge Pump. The charge pump is used to generate a  
gate-supply voltage greater than VBB to drive the source-  
side DMOS gates. A 0.22 µF ceramic capacitor should be  
connected between CP1 and CP2 for pumping purposes.  
A 0.22 µF ceramic capacitor should be connected between  
CP and VBB to act as a reservoir to operate the high-side  
DMOS devices. The CP voltage is internally monitored  
and, in the case of a fault condition, the source outputs of  
the device are disabled.  
EXT MODE  
Decay  
Fast  
0
1
Slow  
Current Regulation. Load current is regulated by an  
internal fixed off-time PWM control circuit. When the  
outputs of the DMOS H bridge are turned on, the current  
increases in the motor winding until it reaches a trip value  
determined by the external sense resistor (RS) and the  
applied analog reference voltage (VREF):  
PHASE Logic. The PHASE input terminal determines if  
the device is operating in the “forward” or “reverse” state.  
PHASE  
OUTA  
Low  
OUTB  
High  
Low  
ITRIP = VREF/10RS  
0
1
At the trip point, the sense comparator resets the source-  
enable latch, turning off the source driver. The load  
inductance then causes the current to recirculate for the  
fixed off-time period. The current path during  
recirculation is determined by the configuration of slow/  
mixed/fast current-decay mode via PFD1 and PFD2.  
High  
ENABLE Logic. The ENABLE input terminal allows  
external PWM. ENABLE high turns on the selected sink-  
source pair. ENABLE low switches off the source driver  
or the source and sink driver, depending on EXT MODE,  
and the load current decays. If ENABLE is kept high, the  
current will rise until it reaches the level set by the internal  
current-control circuit.  
Oscillator. The PWM timer is based on an internal  
oscillator set by a resistor connected from the ROSC  
terminal to VDD. Typical value of 4 MHz is set with a  
51 kresistor. The allowable range of the resistor is from  
20 kto 100 k.  
ENABLE  
Outputs  
Chopped  
On  
f
OSC = 204 x 109/ROSC  
.
0
1
If ROSC is not pulled up to VDD, it must be shorted to  
ground.  
Fixed Off Time. The A3959 is set for a fixed off time of  
96 cycles of the internal oscillator, typically 24 µs with a  
4 MHz oscillator.  
www.allegromicro.com  
5

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