timing analysis, user programming, and debug and diagnostic
probe capabilities. In addition, Designer 3.0 provides the
DirectTime™ tool which provides deterministic as well as
controllable timing. DirectTime allows the designer to
specify the performance requirements of individual paths and
system clock(s). Using these specifications, the software will
automatically optimize the placement and routing of the logic
to meet these constraints. Included with Designer 3.0 is
provides CAE interfaces to Cadence, Escalade, Exemplar
Logic, IST, Mentor Graphics‚ OrCAD, Synopsys, and
Viewlogic design environments. Additional development
tools are supported through Actel’s Industry Alliance
Program, including DATA I/O (ABEL FPGA) and MINC.
Actel’s FPGAs are an ideal solution for shortening the system
design and development cycle and offers a cost-effective
alternative for low volume production runs. The 3200DX
devices are an excellent choice for integrating logic that is
currently implemented in TTL, PALs, CPLDs and FPGAs.
Some example applications include high-speed controllers
and address decoding, peripheral bus interfaces, DSP, and
co-processor functions.
™
Actel’s ACTgen Macro Builder. ACTgen allows the
designer to quickly build fast, efficient logic functions such
as counters, adders, FIFOs, and RAM.
The Designer Series tools provide designers the capability to
move up to High-Level Description Languages, such as
VHDL and Verilog, or use schematic design entry with
interfaces to most EDA tools. Designer Series 3.0 is
supported on the following development platforms: 386/486
and Pentium PC, Sun‚ and HP‚ workstations. The software
D e v i c e R e s o u r c e s
User I/Os
PLCC
84-pin
PQFP
160-pin
PQFP
208-pin
PQFP
240-pin
TQFP
176-pin
BGA
225-pin
BGA
313-pin
Device Series
A3265DX
72
72
—
—
—
—
125
125
125
—
—
156
176
176
—
—
—
126
151
151
—
—
156
176
TBD
—
—
—
A32100DX
A32140DX
A32200DX
A32300DX
A32400DX
—
—
TBD
TBD
TBD
206
254
TBD
—
—
—
—
—
—
Package Definitions (Consult your local Actel Sales Representative for product availability.)
PLCC = Plastic Leaded Chip Carrier, PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, BGA = Ball Grid Array
O r d e r i n g I n f o r m a t i o n
A32200
DX –
1
PQ
208
C
Application (Temperature Range)
C = Commercial (0 to +70°C)
I
= Industrial (–40 to +85°C)
PP = Pre-Production
Package Lead Count
Package Type
PL = Plastic J-Leaded Chip Carrier
PQ = Plastic Quad Flatpack
TQ = Thin (1.4 mm) Quad Flatpack
RQ = Power Quad Flatpack
BG = Ball Grid Array
Speed Grade
Blank = Standard Speed
–1 = Approximately 15% faster than Standard
–2 = Approximately 25% faster than Standard
Sub Family
Part Number
2