3 2 0 0 D X F i e l d P r o g r a m m a b l e G a t e A r r a y s – T h e S y s t e m L o g i c I n t e g r a t o r ™ F a m i l y
C lo c k N e t w o r k s
Two low-skew, high fanout clock distribution networks are
provided in each 3200DX device. These networks are
referred to as CLK0 and CLK1. Each network has a clock
module (CLKMOD) that selects the source of the clock
signal and may be driven as follows:
CLKB
CLKA
CLKINB
CLKINA
FROM
PADS
S0
S1
INTERNAL
SIGNAL
CLKMOD
1. Externally from the CLKA pad
2. Externally from the CLKB pad
3. Internally from the CLKINA input
4. Internally from the CLKINB input
CLKO(17)
CLKO(16)
CLKO(15)
CLOCK
DRIVERS
The clock modules are located in the top row of I/O modules.
Clock drivers and a dedicated horizontal clock track are
located in each horizontal routing channel.
The user controls the clock module by selecting one of two
clock macros from the macro library. The macro CLKBUF is
used to connect one of the two external clock pins to a clock
network, and the macro CLKINT is used to connect an
internally generated clock signal to a clock network. Since
both clock networks are identical, the user does not care
whether CLK0 or CLK1 is being used. The clock input pads
may also be used as normal I/Os, bypassing the clock
networks (see Figure 7).
CLKO(2)
CLKO(1)
CLOCK TRACKS
Figure 7 • Clock Networks
The 3200DX devices which contain SRAM modules (all
except A3265DX and A32140DX) have four additional
register control resources, called Quadrant Clock Networks
(Figure 8). Each quadrant clock provides a local, high-fanout
resource to the contiguous logic modules within its quadrant
of the device. Quadrant clock signals can originate from
specific I/O pins or from the internal array and can be used as
a secondary register clock, register clear, or output enable.
T e s t C ir c u it r y
The 3200DX provides two modes of device and/or
board-level testing; JTAG 1149.1 Boundary Scan Testing
and Actel’s Actionprobe® test facility. Once a 3200DX
device has been programmed, the Actionprobe test facility
QCLKA
QCLKC
Quad
Quad
Clock
Module
Clock
Module
QCLK1
QCLK3
QCLKB
QCLKD
*QCLK1IN
*QCLK3IN
S0 S1
S1 S0
Quad
Clock
Quad
Clock
QCLK2
QCLK4
Module
Module
*QCLK2IN
*QCLK4IN
S0 S1
S1 S0
*QCLK1IN, QCLK2IN, QCLK3IN, and QCKL4IN are internally generated signals.
Figure 8 • Quadrant Clock Network
7