Datasheet > A32200DX-1BGG225C

A32200DX-1BGG225C

更新时间： 2022-12-01 19:18:12

品牌	Logo	应用领域
ACTEL		栅
页数	文件大小	规格书
22页	217K
描述
Field Programmable Gate Array, 1230 CLBs, 20000 Gates, CMOS, PBGA225, BGA-225

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3 2 0 0 D X F i e l d P r o g r a m m a b l e G a t e A r r a y s – T h e S y s t e m L o g i c I n t e g r a t o r ™ F a m i l y

analogous to the wide-input AND term in a CPLD or PAL

device. The output of the D-module has a programmable

inverter for active HIGH or LOW assertion. The D-module

output is hardwired to an output pin or can be fed back into

the array to be incorporated into other logic.

7 inputs

Du a l-P o r t S R AM Mo d u le s

hardwire to I/O

The 3200DX dual-port SRAM modules have been optimized

for synchronous or asynchronous applications. The SRAM

modules are arranged in 256 bit blocks which can be

configured as 32 x 8 or 64 x 4 (refer to Table 1 for the number

of SRAM modules within a particular device). The SRAM

module block structure allows them to be cascaded together

to form user-definable memory spaces. Resources within the

3200DX architecture allow the SRAM modules to be

cascaded together without incurring an additional delay

penalty. A block diagram of the 3200DX dual-port SRAM

block is shown in Figure 4.

Programmable

inverter

feedback to array

Figure 3 • D-Module Implementation

and read ports of the SRAM block have eight data inputs

(WD[7:0]) and eight outputs (RD[7:0]). The SRAM block

outputs are connected to segmented vertical routing tracks.

The 3200DX SRAM blocks are true dual-port structures

containing independent READ and WRITE logic. The

SRAM blocks contain six bits of read and write addressing

(RDAD[5:0] and WRAD[5:0] respectively) for 64x4 bit

blocks. When configured in byte mode, the highest order

address bits (RDAD5 and WRAD5) are not used. The read

and write ports of the SRAM blocks contain independent

clocks (RCLK and WCLK) with programmable polarities

offering active HIGH or LOW implementation. The write

The 3200DX dual-port SRAM blocks are ideal for

high-speed buffered applications such as DMA controllers

and FIFO and LIFO queues. Actel’s ACTgen Macro Builder

provides the capability to quickly design memory elements,

such as FIFOs, LIFOs, and RAM arrays which can be

included in any 3200DX design. Additionally, unused SRAM

blocks can be used to implement registers for other logic

within the design.

WD[7:0]

Latches

[7:0]

[5:0]

RDAD[5:0]

SRAM Module

32 x 8 or 64 x 4

Latches

Read

Port

Logic

Write

Port

Logic

(256 bits)

WRAD[5:0]

[5:0]

LEN

REN

Read

Logic

Latches

RCLK

MODE

BLKEN

WEN

RD[7:0]

Write

Logic

Routing Tracks

WCLK

Figure 4 • Dual-Port SRAM Module

1 2 3 456 7 8...22

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与A32200DX-1BGG225C相关器件

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