SmartFusion Device Family Overview
ProASIC3 FPGA Fabric
The SmartFusion family, based on the proven, low power, firm-error immune ProASIC®3 flash FPGA
architecture, benefits from the advantages only flash-based devices offer:
Reduced Cost of Ownership
Advantages to the designer extend beyond low unit cost, high performance, and ease of use. Flash-
based SmartFusion devices are live at power-up and do not need to be loaded from an external boot
PROM at each power-up. On-board security mechanisms prevent access to the programming
information and enable secure remote updates of the FPGA logic. Designers can perform secure remote
in-system programming (ISP) to support future design iterations and critical field upgrades, with
confidence that valuable IP cannot be compromised or copied. Secure ISP can be performed using the
industry standard AES algorithm with MAC data authentication on the device.
Low Power
Flash-based SmartFusion devices exhibit power characteristics similar to those of an ASIC, making them
an ideal choice for power-sensitive applications. With SmartFusion devices, there is no power-on current
and no high current transition, both of which are common with SRAM-based FPGAs.
SmartFusion devices also have low dynamic power consumption and support very low power time-
keeping mode, offering further power savings.
Security
As the nonvolatile, flash-based SmartFusion family requires no boot PROM, there is no vulnerable
external bitstream. SmartFusion devices incorporate FlashLock®, which provides a unique combination
of reprogrammability and design security without external overhead, advantages that only an FPGA with
nonvolatile flash programming can offer.
SmartFusion devices utilize a 128-bit flash-based key lock and a separate AES key to secure
programmed IP and configuration data. The FlashROM data in Fusion devices can also be encrypted
prior to loading. Additionally, the flash memory blocks can be programmed during runtime using the AES-
128 block cipher encryption standard (FIPS Publication 192).
SmartFusion devices with AES-based security allow for secure remote field updates over public
networks, such as the Internet, and ensure that valuable IP remains out of the hands of system
overbuilders, system cloners, and IP thieves. As an additional security measure, the FPGA configuration
data of a programmed Fusion device cannot be read back, although secure design verification is
possible. During design, the user controls and defines both internal and external access to the flash
memory blocks.
Security, built into the FPGA fabric, is an inherent component of the SmartFusion family. The flash cells
are located beneath seven metal layers, and many device design and layout techniques have been used
to make invasive attacks extremely difficult. SmartFusion with FlashLock and AES security is unique in
being highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected, making
secure remote ISP possible. A SmartFusion device provides the most impenetrable security for
programmable logic designs.
Single Chip
Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the
configuration data is an inherent part of the FPGA structure, and no external configuration data needs to
be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based SmartFusion
FPGAs do not require system configuration components such as electrically erasable programmable
read-only memories (EEPROMs) or microcontrollers to load device configuration data during power-up.
This reduces bill-of-materials costs and PCB area, and increases system security and reliability.
Live at Power-Up
Flash-based SmartFusion devices are live at power-up (LAPU). LAPU SmartFusion devices greatly
simplify total system design and reduce total system cost by eliminating the need for complex
programmable logic devices (CPLDs). SmartFusion LAPU clocking (PLLs) replaces off-chip clocking
resources. In addition, glitches and brownouts in system power will not corrupt the SmartFusion device
flash configuration. Unlike SRAM-based FPGAs, the device will not have to be reloaded when system
power is restored. This enables reduction or complete removal of expensive voltage monitor and
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