A29L160A Series
Characteristics" section contains timing specification tables
and timing diagrams for write operations.
Word/Byte Configuration
The
pin determines whether the I/O pins I/O15-I/O0
BYTE
Program and Erase Operation Status
operate in the byte or word configuration. If the
pin is
BYTE
set at logic ”1”, the device is in word configuration, I/O15-I/O0
are active and controlled by and
During an erase or program operation, the system may
check the status of the operation by reading the status bits
on I/O7 - I/O0. Standard read cycle timings and ICC read
specifications apply. Refer to "Write Operation Status" for
more information, and to each AC Characteristics section for
timing diagrams.
.
OE
CE
If the
pin is set at logic “0”, the device is in byte
BYTE
configuration, and only I/O0-I/O7 are active and controlled by
and . I/O8-I/O14 are tri-stated, and I/O15 pin is used
CE
OE
as an input for the LSB(A-1) address function.
Standby Mode
Requirements for Reading Array Data
When the system is not reading or writing to the device, it
can place the device in the standby mode. In this mode,
current consumption is greatly reduced, and the outputs are
To read array data from the outputs, the system must drive
the
and
pins to VIL.
is the power control and
CE
OE
CE
placed in the high impedance state, independent of the
input.
OE
selects the device.
is the output control and gates array
OE
data to the output pins.
should remain at VIH all the time
WE
during read operation. The
The device enters the CMOS standby mode when the
&
CE
pin determines whether
BYTE
pins are both held at VCC ± 0.3V. (Note that this is a
RESET
more restricted voltage range than VIH.) If
the device outputs array data in words and bytes. The
internal state machine is set for reading array data upon
device power-up, or after a hardware reset. This ensures that
no spurious alteration of the memory content occurs during
the power transition. No command is necessary in this mode
to obtain array data. Standard microprocessor read cycles
that assert valid addresses on the device address inputs
produce valid data on the device data outputs. The device
remains enabled for read access until the command register
contents are altered.
See "Reading Array Data" for more information. Refer to the
AC Read Operations table for timing specifications and to the
Read Operations Timings diagram for the timing waveforms,
lCC1 in the DC Characteristics table represents the active
current specification for reading array data.
and
CE
RESET
are held at VIH, but not within VCC ± 0.3V, the device will be
in the standby mode, but the standby current will be greater.
The device requires the standard access time (tCE) before it
is ready to read data.
If the device is deselected during erasure or programming,
the device draws active current until the operation is
completed.
ICC3 and ICC4 in the DC Characteristics tables represent the
standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy
consumption. The device automatically enables this mode
when addresses remain stable for tACC +30ns. The automatic
Writing Commands/Command Sequences
sleep mode is independent of the
,
and
control
OE
WE
CE
signals. Standard address access timings provide new data
when addresses are changed. While in sleep mode, output
data is latched and always available to the system. ICC4 in the
DC Characteristics table represents the automatic sleep
mode current specification.
To write a command or command sequence (which includes
programming data to the device and erasing sectors of
memory), the system must drive
and
to VIL, and
CE
WE
to VIH. For program operations, the
pin
BYTE
OE
determines whether the device accepts program data in
bytes or words, Refer to “Word/Byte Configuration” for more
information. The device features an Unlock Bypass mode to
facilitate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are required to
program a word or byte, instead of four. The “
Output Disable Mode
When the
input is at VIH, output from the device is
OE
disabled. The output pins are placed in the high impedance
state.
Word / Byte Program Command Sequence” section has
details on programming data to the device using both
standard and Unlock Bypass command sequence. An erase
operation can erase one sector, multiple sectors, or the
entire device. The Sector Address Tables indicate the
address range that each sector occupies. A "sector address"
consists of the address inputs required to uniquely select a
sector. See the "Command Definitions" section for details on
erasing a sector or the entire chip, or suspending/resuming
the erase operation.
After the system writes the autoselect command sequence,
the device enters the autoselect mode. The system can then
read autoselect codes from the internal register (which is
separate from the memory array) on I/O7 - I/O0. Standard
read cycle timings apply in this mode. Refer to the
"Autoselect Mode" and "Autoselect Command Sequence"
sections for more information.
: Hardware Reset Pin
RESET
The
pin provides a hardware method of resetting
RESET
the device to reading array data. When the system drives the
pin low for at least a period of tRP, the device
RESET
immediately terminates any operation in progress, tristates
all data output pins, and ignores all read/write attempts for
the duration of the
pulse. The device also resets the
RESET
internal state machine to reading array data. The operation
that was interrupted should be reinitiated once the device is
ready to accept another command sequence, to ensure data
integrity.
Current is reduced for the duration of the
pulse.
RESET
When
is held at VSS ± 0.3V, the device draws
RESET
CMOS standby current (ICC4 ). If
within VSS ± 0.3V, the standby current will be greater.
is held at VIL but not
RESET
ICC2 in the DC Characteristics table represents the active
current specification for the write mode. The "AC
(May, 2005, Version 0.1)
6
AMIC Technology, Corp.
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