Datasheet > A29DL323UG-80IF

A29DL323UG-80IF

更新时间： 2024-01-11 23:28:07

品牌	Logo	应用领域
联笙电子 - AMICC		内存集成电路闪存
页数	文件大小	规格书
57页	711K
描述
Flash, 2MX16, 80ns, PBGA48

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技术参数
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A29DL323UG-80IF 技术参数

是否Rohs认证：	符合	生命周期：	Contact Manufacturer
包装说明：	FBGA, BGA48,6X8,32	Reach Compliance Code：	unknown
风险等级：	5.69	最长访问时间：	80 ns
备用内存宽度：	8	启动块：	BOTTOM
命令用户界面：	YES	通用闪存接口：	YES
数据轮询：	YES	JESD-30 代码：	R-PBGA-B48
内存密度：	33554432 bit	内存集成电路类型：	FLASH
内存宽度：	16	部门数/规模：	8,63
端子数量：	48	字数：	2097152 words
字数代码：	2000000	最高工作温度：	85 °C
最低工作温度：	-25 °C	组织：	2MX16
封装主体材料：	PLASTIC/EPOXY	封装代码：	FBGA
封装等效代码：	BGA48,6X8,32	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, FINE PITCH	并行/串行：	PARALLEL
电源：	3/3.3 V	认证状态：	Not Qualified
就绪/忙碌：	YES	部门规模：	8K,64K
最大待机电流：	0.000005 A	子类别：	Flash Memories
最大压摆率：	0.045 mA	表面贴装：	YES
技术：	CMOS	温度等级：	OTHER
端子形式：	BALL	端子节距：	0.8 mm
端子位置：	BOTTOM	切换位：	YES
类型：	NOR TYPE	Base Number Matches：	1

A29DL323UG-80IF 数据手册

A29DL32x Series

The

pin may be tied to the system reset circuitry. A

RESET

Automatic Sleep Mode

system reset would thus also reset the Flash memory,

enabling the system to read the boot-up firmware from the

Flash memory.

The automatic sleep mode minimizes Flash device energy

consumption. The device automatically enables this mode

when addresses remain stable for t^ACC+30ns. The automatic

is asserted during a program or erase operation,

RESET

sleep mode is independent of the

and

control

the RY/

pin remains a “0” (busy) until the internal reset

signals. Standard address access timings provide new data

when addresses are changed. While in sleep mode, output

data is latched and always available to the system. I^CC4in the

DC Characteristics table represents the automatic sleep

mode current specification.

operation is complete, which requires a time t^READY(during

Embedded Algorithms). The system can thus monitor

RY/

complete. If

to determine whether the reset operation is

is asserted when a program or erase

RESET

operation is not executing (RY/

operation is completed within a time of t^READY(not during

Embedded Algorithms). The system can read data t^RHafter

pin is “1”), the reset

: Hardware Reset Pin

RESET

The

pin provides a hardware method of resetting

RESET

the device to reading array data. When the system drives the

pin low for at least a period of tRP, the device

the

pin return to VIH.

RESET

Refer to the AC Characteristics tables for

parameters and diagram.

RESET

immediately terminates any operation in progress, tristates

all data output pins, and ignores all read/write attempts for

Output Disable Mode

the duration of the

pulse. The device also resets the

RESET

When the

input is at VIH, output from the device is

internal state machine to reading array data. The operation

that was interrupted should be reinitiated once the device is

ready to accept another command sequence, to ensure data

integrity.

disabled. The output pins are placed in the high impedance

state.

Current is reduced for the duration of the

pulse.

RESET

When

is held at VSS ± 0.3V, the device draws

RESET

CMOS standby current (I^CC4). If

is held at VIL but not

RESET

within VSS ± 0.3V, the standby current will be greater.

Table 2. A29DL32x Device Bank Divisions

Device

Part Number

Bank 1

Sector Sizes

Bank 2

Sector Sizes

Megabits

Eight 8 Kbyte/4 Kword,

seven 64 Kbyte/32 Kword

Fifty-six

64 Kbyte/32 Kword

A29DL322

4 Mbit

28 Mbit

Eight 8 Kbyte/4 Kword,

fifteen 64 Kbyte/32 Kword

Forty-eight

64 Kbyte/32 Kword

A29DL323

A29DL324

8 Mbit

24 Mbit

16 Mbit

Eight 8 Kbyte/4 Kword,

Thirty one 64 Kbyte/32 Kword

Thirty-two

64 Kbyte/32 Kword

16 Mbit

(November, 2007, Version 1.2)

AMIC Technology, Corp.

1...5 6 789 10 11...57

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与A29DL323UG-80IF相关器件

型号	品牌	描述	获取价格	数据表
A29DL323UG-80U	AMICC	Flash, 2MX16, 80ns, PBGA48	获取价格
A29DL323UG-80UF	AMICC	暂无描述	获取价格
A29DL323UG-90	AMICC	32M-Bit CMOS Low Voltage Dual Operation Flash Memory 4M-Byte by 8-Bit (Byte Mode) / 2M-Wor	获取价格
A29DL323UG-90F	AMICC	Flash, 2MX16, 90ns, PBGA48	获取价格
A29DL323UG-90I	AMICC	暂无描述	获取价格
A29DL323UG-90U	AMICC	暂无描述	获取价格

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