A29DL32x Series
The
pin may be tied to the system reset circuitry. A
RESET
sleep mode is independent of the
,
and
control
OE
WE
CE
system reset would thus also reset the Flash memory,
enabling the system to read the boot-up firmware from the
Flash memory.
signals. Standard address access timings provide new data
when addresses are changed. While in sleep mode, output
data is latched and always available to the system. ICC4 in the
DC Characteristics table represents the automatic sleep
mode current specification.
If
is asserted during a program or erase operation,
RESET
the RY/
pin remains a “0” (busy) until the internal reset
BY
operation is complete, which requires a time tREADY (during
Embedded Algorithms). The system can thus monitor
: Hardware Reset Pin
RESET
The
pin provides a hardware method of resetting
RY/
BY
complete. If
to determine whether the reset operation is
RESET
the device to reading array data. When the system drives the
is asserted when a program or erase
RESET
pin low for at least a period of tRP, the device
immediately terminates any operation in progress, tristates
all data output pins, and ignores all read/write attempts for
RESET
operation is not executing (RY/
operation is completed within a time of tREADY (not during
Embedded Algorithms). The system can read data tRH after
pin is “1”), the reset
BY
the duration of the
pulse. The device also resets the
RESET
the
pin return to VIH.
RESET
internal state machine to reading array data. The operation
that was interrupted should be reinitiated once the device is
ready to accept another command sequence, to ensure data
integrity.
Refer to the AC Characteristics tables for
parameters and diagram.
RESET
Output Disable Mode
Current is reduced for the duration of the
pulse.
RESET
When the
input is at VIH, output from the device is
OE
When
is held at VSS ± 0.3V, the device draws
RESET
disabled. The output pins are placed in the high impedance
state.
CMOS standby current (ICC4 ). If
is held at VIL but not
RESET
within VSS ± 0.3V, the standby current will be greater.
Table 2. A29DL32x Device Bank Divisions
Device
Part Number
Bank 1
Sector Sizes
Bank 2
Sector Sizes
Megabits
Megabits
Eight 8 Kbyte/4 Kword,
seven 64 Kbyte/32 Kword
Fifty-six
64 Kbyte/32 Kword
A29DL322
4 Mbit
28 Mbit
Eight 8 Kbyte/4 Kword,
fifteen 64 Kbyte/32 Kword
Forty-eight
64 Kbyte/32 Kword
A29DL323
A29DL324
8 Mbit
24 Mbit
16 Mbit
Eight 8 Kbyte/4 Kword,
Thirty one 64 Kbyte/32 Kword
Thirty-two
64 Kbyte/32 Kword
16 Mbit
PRELIMINARY (May, 2005, Version 0.0)
7
AMIC Technology, Corp.