Datasheet > A29DL164UV-120

A29DL164UV-120

更新时间： 2022-11-26 00:51:33

品牌	Logo	应用领域
联笙电子 - AMICC		闪存
页数	文件大小	规格书
47页	738K
描述
16 Megabit (2M x 8-Bit/1M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory

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A29DL164UV-120 数据手册

A29DL16x Series

The

pin may be tied to the system reset circuitry. A

RESET

sleep mode is independent of the

and

control

system reset would thus also reset the Flash memory,

enabling the system to read the boot-up firmware from the

Flash memory.

signals. Standard address access timings provide new data

when addresses are changed. While in sleep mode, output

data is latched and always available to the system. I^CC4in the

DC Characteristics table represents the automatic sleep

mode current specification.

is asserted during a program or erase operation,

RESET

the RY/

pin remains a “0” (busy) until the internal reset

operation is complete, which requires a time t^READY(during

Embedded Algorithms). The system can thus monitor

: Hardware Reset Pin

RESET

The

pin provides a hardware method of resetting

RY/

complete. If

to determine whether the reset operation is

RESET

the device to reading array data. When the system drives the

is asserted when a program or erase

RESET

pin low for at least a period of tRP, the device

immediately terminates any operation in progress, tristates

all data output pins, and ignores all read/write attempts for

RESET

operation is not executing (RY/

operation is completed within a time of t^READY(not during

Embedded Algorithms). The system can read data t^RHafter

pin is “1”), the reset

the duration of the

pulse. The device also resets the

RESET

the

pin return to VIH.

RESET

internal state machine to reading array data. The operation

that was interrupted should be reinitiated once the device is

ready to accept another command sequence, to ensure data

integrity.

Refer to the AC Characteristics tables for

parameters and diagram.

RESET

Output Disable Mode

Current is reduced for the duration of the

pulse.

RESET

When the

input is at VIH, output from the device is

When

is held at VSS ± 0.3V, the device draws

RESET

disabled. The output pins are placed in the high impedance

state.

CMOS standby current (I^CC4). If

is held at VIL but not

RESET

within VSS ± 0.3V, the standby current will be greater.

Table 2. A29DL16x Device Bank Divisions

Device

Part Number

Bank 1

Sector Sizes

Bank 2

Sector Sizes

Megabits

Eight 8 Kbyte/4 Kword,

three 64 Kbyte/32 Kword

Twenty-eight

64 Kbyte/32 Kword

A29DL162

2 Mbit

14 Mbit

Eight 8 Kbyte/4 Kword,

seven 64 Kbyte/32 Kword

Twenty-four

64 Kbyte/32 Kword

A29DL163

A29DL164

4 Mbit

8 Mbit

12 Mbit

8 Mbit

Eight 8 Kbyte/4 Kword,

fifteen 64 Kbyte/32 Kword

Sixteen

64 Kbyte/32 Kword

PRELIMINARY (September, 2004, Version 0.0)

AMIC Technology, Corp.

1...5 6 789 10 11...47

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