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A29001U-55F

更新时间： 2024-01-02 04:27:40
品牌 Logo 应用领域
联笙电子 - AMICC 闪存存储内存集成电路光电二极管
页数 文件大小 规格书
36页 454K
描述
128K X 8 Bit CMOS 5.0 Volt-only, Boot Sector Flash Memory

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中文翻译

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A29001U-55F 技术参数

是否Rohs认证：符合生命周期：Contact Manufacturer
零件包装代码：DIP包装说明：LEAD FREE, PLASTIC, DIP-32
针数：32Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.32.00.51
风险等级：5.55Is Samacsys：N
最长访问时间：55 ns其他特性：BOTTOM BOOT SECTOR
启动块：BOTTOM命令用户界面：YES
数据轮询：YESJESD-30 代码：R-PDIP-T32
长度：41.91 mm内存密度：1048576 bit
内存集成电路类型：FLASH内存宽度：8
功能数量：1部门数/规模：1,2,1,3
端子数量：32字数：131072 words
字数代码：128000工作模式：ASYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：128KX8封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装等效代码：DIP32,.6
封装形状：RECTANGULAR封装形式：IN-LINE
并行/串行：PARALLEL电源：5 V
编程电压：5 V认证状态：Not Qualified
座面最大高度：5.334 mm部门规模：8K,4K,16K,32K
最大待机电流：0.000005 A子类别：Flash Memories
最大压摆率：0.04 mA最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：NO技术：CMOS
温度等级：COMMERCIAL端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
切换位：YES类型：NOR TYPE
宽度：15.24 mmBase Number Matches：1

A29001U-55F 数据手册

 浏览型号A29001U-55F的Datasheet PDF文件第7页浏览型号A29001U-55F的Datasheet PDF文件第8页浏览型号A29001U-55F的Datasheet PDF文件第9页浏览型号A29001U-55F的Datasheet PDF文件第11页浏览型号A29001U-55F的Datasheet PDF文件第12页浏览型号A29001U-55F的Datasheet PDF文件第13页 
A29001/A290011 Series  
Figure 3 illustrates the algorithm for the erase operation.  
See the Erase/Program Operations tables in "AC  
Characteristics" for parameters, and to the Chip/Sector  
Erase Operation Timings for timing waveforms.  
START  
Sector Erase Command Sequence  
Write Program  
Command  
Sequence  
Sector erase is a six-bus-cycle operation. The sector  
erase command sequence is initiated by writing two  
unlock cycles, followed by a set-up command. Two  
additional unlock write cycles are then followed by the  
address of the sector to be erased, and the sector erase  
command. The Command Definitions table shows the  
address and data requirements for the sector erase  
command sequence.  
Data Poll  
from System  
Embedded  
Program  
algorithm in  
progress  
The device does not require the system to preprogram the  
memory prior to erase. The Embedded Erase algorithm  
automatically programs and verifies the sector for an all  
zero data pattern prior to electrical erase. The system is  
not required to provide any controls or timings during  
these operations.  
Verify Data ?  
Yes  
No  
After the command sequence is written, a sector erase  
time-out of 50µs begins. During the time-out period,  
additional sector addresses and sector erase commands  
may be written. Loading the sector erase buffer may be  
done in any sequence, and the number of sectors may be  
from one sector to all sectors. The time between these  
additional cycles must be less than 50µs, otherwise the  
last address and command might not be accepted, and  
erasure may begin. It is recommended that processor  
interrupts be disabled during this time to ensure all  
commands are accepted. The interrupts can be re-  
enabled after the last Sector Erase command is written. If  
the time between additional sector erase commands can  
be assumed to be less than 50µs, the system need not  
monitor I/O3. Any command other than Sector Erase or  
Erase Suspend during the time-out period resets the  
device to reading array data. The system must rewrite the  
command sequence and any additional sector addresses  
and commands.  
Increment Address  
Last Address ?  
Yes  
Programming  
Completed  
Note : See the appropriate Command Definitions table for  
program command sequence.  
The system can monitor I/O3 to determine if the sector  
erase timer has timed out. (See the " I/O3: Sector Erase  
Timer" section.) The time-out begins from the rising edge  
Figure 2. Program Operation  
of the final  
pulse in the command sequence.  
WE  
Chip Erase Command Sequence  
Once the sector erase operation has begun, only the  
Erase Suspend command is valid. All other commands are  
ignored.  
Chip erase is a six-bus-cycle operation. The chip erase  
command sequence is initiated by writing two unlock  
cycles, followed by a set-up command. Two additional  
unlock write cycles are then followed by the chip erase  
command, which in turn invokes the Embedded Erase  
algorithm. The device does not require the system to  
preprogram prior to erase. The Embedded Erase  
algorithm automatically preprograms and verifies the  
entire memory for an all zero data pattern prior to electrical  
erase. The system is not required to provide any controls  
or timings during these operations. The Command  
Definitions table shows the address and data  
requirements for the chip erase command sequence.  
Any commands written to the chip during the Embedded  
Erase algorithm are ignored.  
When the Embedded Erase algorithm is complete, the  
device returns to reading array data and addresses are no  
longer latched. The system can determine the status of  
the erase operation by using I/O7, I/O6, or I/O2. Refer to  
"Write Operation Status" for information on these status  
bits. Figure 3 illustrates the algorithm for the erase  
operation. Refer to the Erase/Program Operations tables  
in the "AC Characteristics" section for parameters, and to  
the Sector Erase Operations Timing diagram for timing  
waveforms.  
Erase Suspend/Erase Resume Commands  
The Erase Suspend command allows the system to  
interrupt a sector erase operation and then read data from,  
or program data to, any sector not selected for erasure.  
This command is valid only during the sector erase  
operation, including the 50µs time-out period during the  
sector erase command sequence. The Erase Suspend  
The system can determine the status of the erase  
operation by using I/O7, I/O6, or I/O2. See "Write Operation  
Status" for information on these status bits.  
When the Embedded Erase algorithm is complete, the  
device returns to reading array data and addresses are no  
longer latched.  
(December, 2004, Version 1.3)  
9
AMIC Technology, Corp.  
1...78910111213...36

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