A29001B/A290011B Series
128K X 8 Bit CMOS 5.0 Volt-only,
Boot Sector Flash Memory
Preliminary
Features
Minimum 100,000 program/erase cycles per sector
20-year data retention at 125ºC
5.0V ± 10% for read and write operations
Access time:
- Reliable operation for the life of the system
Compatible with JEDEC-standards
- 55ns (max.)
Current:
- Pinout and software compatible with single-power-
supply Flash memory standard
- Superior inadvertent write protection
- 20mA typical active read current
- 30mA typical program/erase current
- 6μA typical CMOS standby
Flexible sector architecture
Polling and toggle bits
Data
- 8 Kbyte/ 4 KbyteX2/ 16 Kbyte/ 32 KbyteX3 sectors
- Any combination of sectors can be erased
- Supports full chip erase
- Provides a software method of detecting completion
of program or erase operations
Erase Suspend/Erase Resume
- Sector protection:
- Suspends a sector erase operation to read data from,
or program data to, a non-erasing sector, then
resumes the erase operation
A hardware method of protecting sectors to prevent
any inadvertent program or erase operations within
that sector
Hardware reset pin (
)
RESET
Top or bottom boot block configurations available
Embedded Erase Algorithms
- Hardware method to reset the device to reading array
data (not available on A290011B)
Industrial operating temperature range: -40°C to +85°C
for – U
Package options
- Embedded Erase algorithm will automatically erase
the entire chip or any combination of designated
sectors and verify the erased sectors
- Embedded Program algorithm automatically writes
and verifies bytes at specified addresses
- 32-pin P-DIP, PLCC or TSOP
- All Pb-free (Lead-free) products are RoHS2.0 compliant
General Description
The A29001B is a 5.0 volt-only Flash memory organized as
131,072 bytes of 8 bits each. The A29001B offers the
The A29001B is entirely software command set compatible
with the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register contents
serve as input to an internal state-machine that controls the
erase and programming circuitry. Write cycles also
internally latch addresses and data needed for the
programming and erase operations. Reading data out of
the device is similar to reading from other Flash or EPROM
devices.
Device programming occurs by writing the proper program
command sequence. This initiates the Embedded Program
algorithm - an internal algorithm that automatically times
the program pulse widths and verifies proper program
margin.
function, but it is not available on A290011B. The
RESET
128 Kbytes of data are further divided into seven sectors for
flexible sector erase capability. The 8 bits of data appear on
I/O0 - I/O7 while the addresses are input on A0 to A16. The
A29001B is offered in 32-pin PLCC, PDIP and TSOP
packages. This device is designed to be programmed in-
system with the standard system 5.0 volt VCC supply.
Additional 12.0 volt VPP is not required for in-system write
or erase operations. However, the A29001B can also be
programmed in standard EPROM programmers.
The A29001B has the first toggle bit, I/O6, which indicates
whether an Embedded Program or Erase is in progress, or it
is in the Erase Suspend. Besides the I/O6 toggle bit, the
A29001B has a second toggle bit, I/O2, to indicate whether
the addressed sector is being selected for erase. The
A29001B also offers the ability to program in the Erase
Suspend mode. The standard A29001B offers access time
of 55ns allowing high-speed microprocessors to operate
without wait states. To eliminate bus contention the device
Device erasure occurs by executing the proper erase
command sequence. This initiates the Embedded Erase
algorithm
- an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper erase margin.
has separate chip enable (
), write enable (
) and
WE
CE
) controls.
output enable (
OE
The host system can detect whether a program or erase
The device requires only a single 5.0 volt power supply for
both read and write functions. Internally generated and
regulated voltages are provided for the program and erase
operations.
operation is complete by reading the I/O7 (
Polling)
Data
and I/O6 (toggle) status bits. After a program or erase cycle
has been completed, the device is ready to read array data
or accept another command.
PRELIMINARY (June, 2016, Version 0.0)
1
AMIC Technology, Corp.
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