Datasheet > A25L80PO

A25L80PO

更新时间： 2022-12-01 21:28:15

品牌	Logo	应用领域
联笙电子 - AMICC		光电二极管
页数	文件大小	规格书
37页	462K
描述
Flash, 8MX1, PDSO8, 0.150 INCH, MS-012AA, SOP-8

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A25L80PO 数据手册

A25L80P Series

Table 1. Protected Area Sizes

Status Register Content

Memory Content

BP2 Bit

BP1 Bit

BP0 Bit

Protected Area

Unprotected Area

none

All sectors (sixteen sectors: 0 to 15)

All sectors¹(sixteen sectors: 0 to 15)

none

Note: 1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0.

2. The sector 0 include sector 0-0, sector 0-1, sector 0-2 and sector 0-3.

Hold Condition

with Serial Clock (C) being Low, the Hold condition ends

after Serial Clock (C) next goes Low. This is shown in Figure

During the Hold condition, the Serial Data Output (Q) is high

impedance, and Serial Data Input (D) and Serial Clock (C)

are Don’t Care.

The Hold (

) signal is used to pause any serial

HOLD

communications with the device without resetting the

clocking sequence. However, taking this signal Low does not

terminate any Write Status Register, Program or Erase cycle

that is currently in progress.

To enter the Hold condition, the device must be selected,

Normally, the device is kept selected, with Chip Select (

)

with Chip Select ( ) Low.

The Hold condition starts on the falling edge of the Hold

driven Low, for the whole duration of the Hold condition. This

is to ensure that the state of the internal logic remains

unchanged from the moment of entering the Hold condition.

(

) signal, provided that this coincides with Serial Clock

HOLD

The Hold condition ends on the rising edge of the Hold

If Chip Select ( ) goes High while the device is in the Hold

condition, this has the effect of resetting the internal logic of

the device. To restart communication with the device, it is

(

) signal, provided that this coincides with Serial Clock

HOLD

necessary to drive Hold (

) High, and then to drive

HOLD

If the falling edge does not coincide with Serial Clock (C)

being Low, the Hold condition starts after Serial Clock (C)

next goes Low. Similarly, if the rising edge does not coincide

Chip Select ( ) Low. This prevents the device from going

back to the Hold condition.

Figure 3. Hold Condition Activation

HOLD

Hold

Condition

(standard use)

(non-standard use)

(April, 2007, Version 1.5)

AMIC Technology Corp.

1...4 5 678 9 10...37

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