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A25L20PTN-F PDF预览

A25L20PTN-F

更新时间： 2024-01-08 17:02:10
品牌 Logo 应用领域
联笙电子 - AMICC 闪存
页数 文件大小 规格书
43页 544K
描述
Flash Memory

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A25L20PTN-F 技术参数

是否Rohs认证： 符合生命周期：Contact Manufacturer
包装说明：DIP, DIP8,.3Reach Compliance Code：unknown
风险等级：5.62Is Samacsys：N
最大时钟频率 (fCLK)：85 MHz数据保留时间-最小值：20
耐久性：100000 Write/Erase CyclesJESD-30 代码：R-PDIP-T8
长度：9.14 mm内存密度：2097152 bit
内存集成电路类型：FLASH内存宽度：8
功能数量：1端子数量：8
字数：262144 words字数代码：256000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：256KX8
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP8,.3封装形状：RECTANGULAR
封装形式：IN-LINE并行/串行：SERIAL
电源：3/3.3 V编程电压：2.7 V
认证状态：Not Qualified座面最大高度：4.57 mm
串行总线类型：SPI最大待机电流：0.00001 A
子类别：Flash Memories最大压摆率：0.02 mA
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.7 V
表面贴装：NO技术：CMOS
温度等级：INDUSTRIAL端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
类型：NOR TYPE宽度：7.62 mm
写保护：HARDWARE/SOFTWAREBase Number Matches：1

A25L20PTN-F 数据手册

 浏览型号A25L20PTN-F的Datasheet PDF文件第5页浏览型号A25L20PTN-F的Datasheet PDF文件第6页浏览型号A25L20PTN-F的Datasheet PDF文件第7页浏览型号A25L20PTN-F的Datasheet PDF文件第9页浏览型号A25L20PTN-F的Datasheet PDF文件第10页浏览型号A25L20PTN-F的Datasheet PDF文件第11页 
A25L20P/A25L10P/A25L05P Series  
Hold Condition  
The Hold (  
communications with the device without resetting the clocking  
sequence. However, taking this signal Low does not  
terminate any Write Status Register, Program or Erase cycle  
that is currently in progress.  
Serial Clock (C) next goes Low. This is shown in Figure 3.  
During the Hold condition, the Serial Data Output (DO) is high  
impedance, and Serial Data Input (DIO) and Serial Clock (C)  
are Don’t Care.  
) signal is used to pause any serial  
HOLD  
Normally, the device is kept selected, with Chip Select (  
)
S
To enter the Hold condition, the device must be selected, with  
driven Low, for the whole duration of the Hold condition. This  
is to ensure that the state of the internal logic remains  
unchanged from the moment of entering the Hold condition.  
Chip Select ( ) Low.  
S
The Hold condition starts on the falling edge of the Hold  
If Chip Select ( ) goes High while the device is in the Hold  
S
condition, this has the effect of resetting the internal logic of  
the device. To restart communication with the device, it is  
(
) signal, provided that this coincides with Serial Clock  
HOLD  
(C) being Low (as shown in Figure 3.).  
The Hold condition ends on the rising edge of the Hold  
necessary to drive Hold (  
) High, and then to drive  
HOLD  
(
) signal, provided that this coincides with Serial Clock  
HOLD  
Chip Select ( ) Low. This prevents the device from going  
S
(C) being Low.  
If the falling edge does not coincide with Serial Clock (C)  
being Low, the Hold condition starts after Serial Clock (C)  
next goes Low. Similarly, if the rising edge does not coincide  
with Serial Clock (C) being Low, the Hold condition ends after  
back to the Hold condition.  
Figure 3. Hold Condition Activation  
C
HOLD  
Hold  
Hold  
Condition  
Condition  
(standard use)  
(non-standard use)  
(August, 2007, Version 1.0)  
7
AMIC Technology Corp.  
1...567891011...43

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