Datasheet > 存储 > 闪存> A25L10PUO-UF

A25L10PUO-UF

更新时间： 2024-02-13 10:09:08

品牌	Logo	应用领域
联笙电子 - AMICC		闪存
页数	文件大小	规格书
43页	544K
描述
2Mbit / 1Mbit / 512Kbit, Low Voltage, Serial Flash Memory With 85MHz SPI Bus Interface

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技术参数
数据手册

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A25L10PUO-UF 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
包装说明：	DIP, DIP8,.3	Reach Compliance Code：	unknown
风险等级：	5.84	Is Samacsys：	N
最大时钟频率 (fCLK)：	50 MHz	耐久性：	100000 Write/Erase Cycles
JESD-30 代码：	R-PDIP-T8	内存密度：	1048576 bit
内存集成电路类型：	FLASH	内存宽度：	8
端子数量：	8	字数：	131072 words
字数代码：	128000	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	128KX8
封装主体材料：	PLASTIC/EPOXY	封装代码：	DIP
封装等效代码：	DIP8,.3	封装形状：	RECTANGULAR
封装形式：	IN-LINE	并行/串行：	SERIAL
电源：	3/3.3 V	认证状态：	Not Qualified
串行总线类型：	SPI	最大待机电流：	0.00005 A
子类别：	Flash Memories	最大压摆率：	0.02 mA
表面贴装：	NO	技术：	CMOS
温度等级：	INDUSTRIAL	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
类型：	NOR TYPE	写保护：	HARDWARE/SOFTWARE
Base Number Matches：	1

A25L10PUO-UF 数据手册

A25L20P/A25L10P/A25L05P Series

Unless an internal Program, Erase or Write Status Register

cycle is in progress, the device will be in the Standby mode

(this is not the Deep Power-down mode). Driving Chip Select

SIGNAL DESCRIPTION

Serial Data Output (DO). This output signal is used to

transfer data serially out of the device. Data is shifted out on

the falling edge of Serial Clock (C).

The DO pin is also used as an input pin when the Fast Read

Dual Input-Output instruction is executed.

(

) Low enables the device, placing it in the active power

mode.

After Power-up, a falling edge on Chip Select ( ) is required

prior to the start of any instruction.

Serial Data Input (DIO). This input signal is used to transfer

data serially into the device. It receives instructions,

addresses, and the data to be programmed. Values are

latched on the rising edge of Serial Clock (C).

The DIO pin is also used as an output pin when the Fast

Read Dual Output instruction and the Fast Read Dual

Input-Output instruction are executed.

Serial Clock (C). This input signal provides the timing of the

serial interface. Instructions, addresses, or data present at

Serial Data Input (DIO) are latched on the rising edge of

Serial Clock (C). Data on Serial Data Output (DO) changes

after the falling edge of Serial Clock (C).

Hold (

). The Hold (

) signal is used to pause

HOLD

any serial communications with the device without

deselecting the device.

During the Hold condition, the Serial Data Output (DO) is high

impedance, and Serial Data Input (DIO) and Serial Clock (C)

are Don’t Care. To start the Hold condition, the device must

be selected, with Chip Select ( ) driven Low.

Write Protect ( ). The main purpose of this input signal is

to freeze the size of the area of memory that is protected

against program or erase instructions (as specified by the

values in the BP1 and BP0 bits of the Status Register).

Chip Select ( ). When this input signal is High, the device is

deselected and Serial Data Output (DO) is at high impedance.

SPI MODES

falling edge of Serial Clock (C).

These devices can be driven by a microcontroller with its SPI

peripheral running in either of the two following modes:

– CPOL=0, CPHA=0

– CPOL=1, CPHA=1

For these two modes, input data is latched in on the rising

edge of Serial Clock (C), and output data is available from the

The difference between the two modes, as shown in Figure 2,

is the clock polarity when the bus master is in Stand-by mode

and not transferring data:

– C remains at 0 for (CPOL=0, CPHA=0)

– C remains at 1 for (CPOL=1, CPHA=1)

(August, 2007, Version 1.0)

AMIC Technology Corp.

1 2 345 6 7...43

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