Datasheet > A25L080Q4-UF

A25L080Q4-UF

更新时间： 2022-04-25 06:57:39

品牌	Logo	应用领域
联笙电子 - AMICC		闪存
页数	文件大小	规格书
43页	681K
描述
16Mbit Low Voltage, Serial Flash Memory With 100MHz Uniform 4KB Sectors

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A25L080Q4-UF 数据手册

A25L016 Series

Hold Condition

The Hold (

communications with the device without resetting the clocking

sequence. However, taking this signal Low does not

terminate any Write Status Register, Program or Erase cycle

that is currently in progress.

Serial Clock (C) next goes Low. This is shown in Figure 3.

During the Hold condition, the Serial Data Output (DO) is high

impedance, and Serial Data Input (DIO) and Serial Clock (C)

are Don’t Care.

) signal is used to pause any serial

HOLD

Normally, the device is kept selected, with Chip Select (

)

To enter the Hold condition, the device must be selected, with

driven Low, for the whole duration of the Hold condition. This

is to ensure that the state of the internal logic remains

unchanged from the moment of entering the Hold condition.

Chip Select ( ) Low.

The Hold condition starts on the falling edge of the Hold

If Chip Select ( ) goes High while the device is in the Hold

condition, this has the effect of resetting the internal logic of

the device. To restart communication with the device, it is

(

) signal, provided that this coincides with Serial Clock

HOLD

The Hold condition ends on the rising edge of the Hold

necessary to drive Hold (

) High, and then to drive

HOLD

(

) signal, provided that this coincides with Serial Clock

HOLD

Chip Select ( ) Low. This prevents the device from going

If the falling edge does not coincide with Serial Clock (C)

being Low, the Hold condition starts after Serial Clock (C)

next goes Low. Similarly, if the rising edge does not coincide

with Serial Clock (C) being Low, the Hold condition ends after

back to the Hold condition.

Figure 3. Hold Condition Activation

HOLD

Hold

Condition

(standard use)

(non-standard use)

(March, 2012, Version 2.0)

AMIC Technology Corp.

1...5 6 789 10 11...43

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