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A1P-L67201V-60 PDF预览

A1P-L67201V-60

更新时间： 2024-01-11 19:45:24
品牌 Logo 应用领域
TEMIC ATM异步传输模式先进先出芯片
页数 文件大小 规格书
16页 146K
描述
FIFO, 512X9, 60ns, Asynchronous, CMOS, CDIP28, 0.300 INCH, CERAMIC, DIP-28

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A1P-L67201V-60 技术参数

生命周期：Obsolete零件包装代码：DIP
包装说明：,针数：28
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.71风险等级：5.78
最长访问时间：60 ns周期时间：75 ns
JESD-30 代码：R-GDIP-T28内存密度：4608 bit
内存宽度：9功能数量：1
端子数量：28字数：512 words
字数代码：512工作模式：ASYNCHRONOUS
最高工作温度：125 °C最低工作温度：-40 °C
组织：512X9可输出：NO
封装主体材料：CERAMIC, GLASS-SEALED封装形状：RECTANGULAR
封装形式：IN-LINE并行/串行：PARALLEL
认证状态：Not Qualified最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：NO技术：CMOS
温度等级：AUTOMOTIVE端子形式：THROUGH-HOLE
端子位置：DUALBase Number Matches：1

A1P-L67201V-60 数据手册

 浏览型号A1P-L67201V-60的Datasheet PDF文件第3页浏览型号A1P-L67201V-60的Datasheet PDF文件第4页浏览型号A1P-L67201V-60的Datasheet PDF文件第5页浏览型号A1P-L67201V-60的Datasheet PDF文件第7页浏览型号A1P-L67201V-60的Datasheet PDF文件第8页浏览型号A1P-L67201V-60的Datasheet PDF文件第9页 
L 67201/L 67202  
MATRA MHS  
Table 1 : Reset and retransmit  
Single Device Configuration/Width Expansion Mode  
INPUTS  
INTERNAL STATUS  
Read Pointer Write Pointer  
OUTPUTS  
MODE  
RS  
0
RT  
X
XI  
0
EF  
0
FF  
1
HF  
1
Reset  
Location Zero  
Location Zero  
Location Zero  
Unchanged  
Retransmit  
Read/Write  
1
0
0
X
X
X
(4)  
(4)  
1
1
0
Increment  
Increment  
X
X
X
Note : 4. Pointer will increment if flag is high.  
Table 2 : Reset and First Load Truth Table  
Depth Expansion/Compound Expansion Mode  
INPUTS  
INTERNAL STATUS  
OUTPUTS  
MODE  
RS  
0
FL  
0
XI  
(5)  
(5)  
(5)  
Read Pointer  
Write Pointer  
Location Zero  
Location Zero  
X
EF  
FF  
1
Reset First Device  
Reset All Other Devices  
Read/Write  
Location Zero  
Location Zero  
X
0
0
0
1
1
1
X
X
X
Note : 5. XI is connected to XO of previous device.  
See fig. 5.  
Depth Expansion (Daisy Chain) Mode  
Compound Expansion Module  
It is quite simple to apply the two expansion techniques  
described above together to create large FIFO arrays (see  
figure 5).  
The L 67201/202 can be easily adapted for applications  
which require more than 512/1024 words. Figure 4  
demonstrates Depth Expansion using three L 67201/202.  
Any depth can be achieved by adding additional  
67201/202.  
Bidirectional Mode  
The L 67201/202 operate in the Depth Expansion  
configuration if the following conditions are met :  
Applications which require data buffering between two  
systems (each system being capable of Read and Write  
operations) can be created by coupling L 67201/202 as  
shown in figure 6. Care must be taken to ensure that the  
appropriate flag is monitored by each system (i.e. FF is  
monitored on the device on which W is in use ; EF is  
monitored on the device on which R is in use). Both Depth  
Expansion and Width Expansion may be used in this  
mode.  
1. The first device must be designated by connecting the  
First Load (FL) control input to ground.  
2. All other devices must have FL in the high state.  
3. The Expansion Out (XO) pin of each device must be  
connected to the Expansion In (XI) pin of the next  
device. See figure 4.  
4. External logic is needed to generate a composite Full  
Flag (FF) and Empty Flag (EF). This requires that all  
EF’s and all FFs be ØRed (i.e. all must be set to  
generate the correct composite FF or EF). See figure 4.  
Data Flow - Through Modes  
Two types of flow-through modes are permitted : a read  
5. The Retransmit (RT) function and Half-Full Flag (HF) flow-through and a write flow-through mode. In the read  
are not available in the Depth Expansion Mode. flow-through mode (figure 17) the FIFO stack allows a  
6
Rev. C (10/11/95)  
1...3456789...16

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与A1P-L67201V-60相关器件

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A1P-L67202L-55 TEMIC FIFO, 1KX9, 55ns, Asynchronous, CMOS, CDIP28, 0.300 INCH, CERAMIC, DIP-28

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A1P-L67202L-60 TEMIC FIFO, 1KX9, 60ns, Asynchronous, CMOS, CDIP28, 0.300 INCH, CERAMIC, DIP-28

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A1P-L67202L-65 TEMIC FIFO, 1KX9, 65ns, Asynchronous, CMOS, CDIP28, 0.300 INCH, CERAMIC, DIP-28

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A1P-L67202V-55 TEMIC FIFO, 1KX9, 55ns, Asynchronous, CMOS, CDIP28, 0.300 INCH, CERAMIC, DIP-28

获取价格
A1P-L67202V-60 TEMIC FIFO, 1KX9, 60ns, Asynchronous, CMOS, CDIP28, 0.300 INCH, CERAMIC, DIP-28

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