Datasheet > A14100BP-2BG313C

A14100BP-2BG313C

更新时间： 2022-12-02 00:53:48

品牌	Logo	应用领域
ACTEL		栅
页数	文件大小	规格书
40页	1250K
描述
Field Programmable Gate Array, 1377 CLBs, 10000 Gates, 150MHz, 1377-Cell, CMOS, PBGA313, PLASTIC, BGA-313

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A14100BP-2BG313C 数据手册

Accelerator Series FPGAs:

ACT 3 PCI-Compliant Family

Features

•

Highly Predictable, Synthesis-Friendly Architecture

Supports High-Level Design Methodologies.

•

Up to 10,000 Gate Array Equivalent Gates.

Up to 250 MHz On-Chip Performance.

9.0 ns Clock-to-Output.

100% Module Utilization with Automatic Place and Route

Tools.

Deterministic, User-Controllable Timing via DirectTime

Software Tool.

Up to 1,153 Dedicated Flip-Flops.

Up to 228 User-Programmable I/O Pins.

PCI-Compliant I/O Drivers.

VHDL and Verilog-HDL Models for PCI Target, Master, and

Bridge Functions.

Four High-Speed, Low-Skew Clocks.

ACT 3 PCI-Compliant Devices

Device

A1460BP

A14100BP

Capacity

Gate Array Equivalent Gates

PLD Equivalent Gates

TTL Equivalent Packages (40 Gates)

20-Pin PAL Equivalent Packages (100 Gates)

6,000

15,000

150

10,000

25,000

250

100

Logic Modules

S-Module

C-Module

848

432

416

1,377

697

680

Dedicated Flip-Flops

768

168

1,153

228

User I/Os (Maximum)

Packages (By Pin Count)

PQFP

RQFP

TQFP

BGA

160, 208

—

208

—

176

225

313

Performance (Maximum, Worst-Case Commercial)

Chip-to-Chip

97 MHz

63 MHz

110 MHz

150 MHz

9.0 ns

93 MHz

63 MHz

105 MHz

150 MHz

9.5 ns

Accumulators (16-Bit)

Loadable Counter (16-Bit)

Prescaled Loadable Counters (16-Bit)

Datapath, Shift Registers

Clock-to-Output (Pad-to-Pad)

Notes:

1. One flip-flop per S-module, two flip-flops per I/O module.

2. See Product Plan on page 3 for package availability.

3. Based on A1460BP-2, and A14100BP-2.

4. Clock-to-Output + Set-Up

March 1997

12 3 4 5 6 7...40

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