Precision, High Speed, Hall-Effect Angle Sensor IC
with Integrated Diagnostics for Safety-Critical Applications
A1333
OPERATING CHARACTERISTICS: Valid over the full operating voltage and ambient temperature ranges, unless otherwise noted
Characteristics
ELECTRICAL CHARACTERISTICS
Supply Voltage [2]
Symbol
Test Conditions
Min.
Typ.
Max.
Unit[1]
VCC
ICC
Customer supply
4.0
–
–
16.5
19
V
Supply Current
One die, sampling angles
17
mA
dV/dt = 1 V/ms, A1333 sampling enabled,
TA = 25°C
Undervoltage Flag Threshold [3]
VUVD
3.6
–
3.9
V
Supply Zener Clamp Voltage
Reverse Battery Current
VZSUP
IRCC
tPO
ICC = ICC + 3 mA, TA = 25°C
26.5
–
–
–
–
5
V
VRCC = 18 V, TA = 25°C
mA
ms
ms
V
Power-on diagnostics disabled
–
15
45
3.3
–
Power-On Time[4]
tPO_D
Power-on time; CVH self-test and LBIST enabled
TA = 25°C, CBYP = 0.1 µF, 3.3 V interface
–
–
2.97
3.63
Bypass Pin Output Voltage[5]
VBYP
TA = 25°C, CBYP = 0.1 µF, 5.0 V interface enabled
and VCC ≥ 5.0 V
4.0
5.0
5.5
V
SPI AND ABI (UVW) ELECTRICAL SPECIFICATIONS (3.3 V INTERFACE)
Digital Input High Voltage
Digital Input Low Voltage
Output High Voltage
VIH
VIL
MOSI, SCLK, CS pins
2.8
–
–
3.63
0.5
3.63
–
V
V
V
V
MOSI, SCLK, CS pins
–
VOH
VOL
MISO, ABI/UVW pins, CL = 20 pF
MISO, ABI/UVW pins, CL = 20 pF
2.93
–
3.3
0.3
Output Low Voltage
SPI AND ABI (UVW) ELECTRICAL SPECIFICATIONS (5.0 V INTERFACE)
Digital Input High Voltage
Digital Input Low Voltage
Output High Voltage
VIH
VIL
MOSI, SCLK, CS pins
3.75
–
–
5.5
0.5
5.5
–
V
V
V
V
MOSI, SCLK, CS pins
–
4
–
VOH
VOL
MISO, ABI/UVW pins, CL = 20 pF, VCC ≥ 5.0 V
MISO, ABI/UVW pins, CL = 20 pF
5
Output Low Voltage
0.3
SPI INTERFACE SPECIFICATIONS
SPI Clock Frequency[6]
SPI Clock Duty Cycle[6]
SPI Frame Rate[6]
fSCLK
DfSCLK
tSPI
MISO pins, CL = 20 pF
SPICLKDC
0.1
40
–
-
10
60
588
–
MHz
%
5.8
50
–
–
kHz
ns
Chip Select to First SCLK Edge[6]
tCS
Time fromCS going low to SCLK falling edge
Time CS must be high between SPI message
frames
Chip Select Idle Time [6]
tCS_IDLE
200
–
–
ns
Data Output Valid Time[6]
MOSI Setup Time[6]
MOSI Hold Time[6]
tDAV
tSU
Data output valid after SCLK falling edge
Input setup time before SCLK rising edge
Input hold time after SCLK rising edge
–
25
50
5
30
–
–
–
ns
ns
ns
ns
pF
tHD
–
–
SCLK to CS Hold Time[6]
Load Capacitance[6]
tCHD
CL
Hold SCLK high time before CS rising edge
–
–
¯¯¯¯
Loading on digital output (MISO) pin
–
–
20
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Allegro MicroSystems, LLC
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com