Datasheet > A1280A-PL84M

A1280A-PL84M

更新时间： 2024-01-14 16:13:05

品牌	Logo	应用领域
ACTEL		栅可编程逻辑
页数	文件大小	规格书
38页	652K
描述
Field Programmable Gate Array, 1232 CLBs, 8000 Gates, CMOS, PQCC84, PLASTIC, LCC-84

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A1280A-PL84M 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	PLASTIC, LCC-84	Reach Compliance Code：	compliant
风险等级：	5.83	JESD-30 代码：	S-PQCC-J84
JESD-609代码：	e0	长度：	29.3116 mm
湿度敏感等级：	3	可配置逻辑块数量：	1232
等效关口数量：	8000	端子数量：	84
最高工作温度：	125 °C	最低工作温度：	-55 °C
组织：	1232 CLBS, 8000 GATES	封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装形状：	SQUARE
封装形式：	CHIP CARRIER	峰值回流温度（摄氏度）：	225
可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY	认证状态：	Not Qualified
座面最大高度：	4.572 mm	最大供电电压：	5.5 V
最小供电电压：	4.5 V	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	MILITARY	端子面层：	TIN LEAD
端子形式：	J BEND	端子节距：	1.27 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	29.3116 mm

A1280A-PL84M 数据手册

ACT^™2 Family FPGAs

Description

The ACT™ 2 family represents Actel’s second generation of

field programmable gate arrays (FPGAs). The ACT 2 family

presents a two-module architecture, consisting of C-modules

and S-modules. These modules are optimized for both

combinatorial and sequential designs. Based on Actel’s

patented channeled array architecture, the ACT 2 family

provides significant enhancements to gate density and

performance while maintaining downward compatibility

technology. This revolutionary architecture offers gate array

design flexibility, high performance, and fast

time-to-production with user programming. The ACT 2

family is supported by the Designer and Designer Advantage

Systems, which offers automatic pin assignment, validation

of electrical and design rules, automatic placement and

routing, timing analysis, user programming, and diagnostic

probe capabilities. The systems are supported on the

following platforms: 386/486™ PC, Sun^™, and HP^™

workstations. The systems provide CAE interfaces to the

following design environments: Cadence, Viewlogic^®,

Mentor Graphics^®, and OrCAD™.

with the ACT

1 design environment and upward

compatibility with the ACT 3 design environment. The

devices are implemented in silicon gate, 1.0-µm, two-level

metal CMOS, and employ Actel’s PLICE^®antifuse

Ordering Information

A1280

–

176

Application (Temperature Range)

C = Commercial (0 to +70°C)

= Industrial (–40 to +85°C)

M = Military (–55 to +125°C)

B = MIL-STD-883

Package Lead Count

Package Type

PL = Plastic J-Leaded Chip Carrier

PQ = Plastic Quad Flat Pack

CQ = Ceramic Quad Flat Pack

PG = Ceramic Pin Grid Array

TQ = Thin (1.4 mm) Quad Flat Pack

VQ = Very Thin (1.0 mm) Quad Flat Pack

Speed Grade

Blank = Standard Speed

–1 = Approximately 15% faster than Standard

–2 = Approximately 25% faster than Standard

Die Revision

A = 1.0-µm CMOS process

Part Number

A1225 = 2500 Gates

A1240 = 4000 Gates

A1280 = 8000 Gates

v4.0

123 4 5 6 7...38

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与A1280A-PL84M相关器件

型号	品牌	描述	获取价格	数据表
A1280A-PLG160B	MICROSEMI	ACT 2 Family FPGAs	获取价格
A1280A-PLG160C	MICROSEMI	ACT 2 Family FPGAs	获取价格
A1280A-PLG160I	MICROSEMI	ACT 2 Family FPGAs	获取价格
A1280A-PLG160M	MICROSEMI	ACT 2 Family FPGAs	获取价格
A1280A-PLG176B	MICROSEMI	ACT 2 Family FPGAs	获取价格
A1280A-PLG176C	MICROSEMI	ACT 2 Family FPGAs	获取价格

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