A1280A-2PGG176B

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A1280A-2PGG176B 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
包装说明：	PGA, PGA176,15X15	Reach Compliance Code：	compliant
风险等级：	5.83	最大时钟频率：	85 MHz
JESD-30 代码：	S-XPGA-P176	输入次数：	140
逻辑单元数量：	1232	输出次数：	140
端子数量：	176	最高工作温度：	125 °C
最低工作温度：	-55 °C	封装主体材料：	CERAMIC
封装代码：	PGA	封装等效代码：	PGA176,15X15
封装形状：	SQUARE	封装形式：	GRID ARRAY
电源：	5 V	可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY
认证状态：	Not Qualified	子类别：	Field Programmable Gate Arrays
标称供电电压：	5 V	表面贴装：	NO
技术：	CMOS	温度等级：	MILITARY
端子形式：	PIN/PEG	端子节距：	2.54 mm
端子位置：	PERPENDICULAR	Base Number Matches：	1

1 – ACT 2 Family Overview

General Description

The ACT 2 family represents Actel’s second generation of field programmable gate arrays

(FPGAs). The ACT 2 family presents a two-module architecture, consisting of C-modules and S-

modules. These modules are optimized for both combinatorial and sequential designs. Based on Actel’s

patented channeled array architecture, the ACT 2 family provides significant enhancements to gate

density and performance while maintaining downward compatibility with the ACT 1 design environment

and upward compatibility with the ACT 3 design environment. The devices are implemented in silicon

gate, 1.0-μm, two-level metal CMOS, and employ Actel’s PLICE® antifuse technology. This revolutionary

architecture offers gate array design flexibility, high performance, and fast time-to-production with user

programming. The ACT 2 family is supported by the Designer and Designer Advantage Systems, which

offers automatic pin assignment, validation of electrical and design rules, automatic placement and

routing, timing analysis, user programming, and diagnostic probe capabilities. The systems are

supported on the following platforms: 386/486™ PC, Sun™, and HP™ workstations. The systems

provide CAE interfaces to the following design environments: Cadence, Viewlogic^®, Mentor Graphics ,

and OrCAD™.

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