A1240A-2TQG176M

更新时间： 2024-02-26 22:14:42

阅读下载

获取价格

如果您发现信息不准确，欢迎纠错

A1240A-2TQG176M 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
包装说明：	1.40 MM, TQFP-176	Reach Compliance Code：	compliant
风险等级：	5.76	其他特性：	MAX 104 I/OS
最大时钟频率：	100 MHz	CLB-Max的组合延迟：	3.8 ns
JESD-30 代码：	S-PQFP-G176	JESD-609代码：	e3
长度：	24 mm	湿度敏感等级：	3
可配置逻辑块数量：	684	等效关口数量：	4000
输入次数：	104	逻辑单元数量：	684
输出次数：	104	端子数量：	176
最高工作温度：	70 °C	最低工作温度：
组织：	684 CLBS, 4000 GATES	封装主体材料：	PLASTIC/EPOXY
封装代码：	LFQFP	封装等效代码：	QFP176,1.0SQ,20
封装形状：	SQUARE	封装形式：	FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	260	电源：	5 V
可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY	认证状态：	Not Qualified
座面最大高度：	1.6 mm	子类别：	Field Programmable Gate Arrays
最大供电电压：	5.25 V	最小供电电压：	4.75 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	MATTE TIN	端子形式：	GULL WING
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	40	宽度：	24 mm
Base Number Matches：	1

1 – ACT 2 Family Overview

General Description

The ACT 2 family represents Actel’s second generation of field programmable gate arrays

(FPGAs). The ACT 2 family presents a two-module architecture, consisting of C-modules and S-

modules. These modules are optimized for both combinatorial and sequential designs. Based on Actel’s

patented channeled array architecture, the ACT 2 family provides significant enhancements to gate

density and performance while maintaining downward compatibility with the ACT 1 design environment

and upward compatibility with the ACT 3 design environment. The devices are implemented in silicon

gate, 1.0-μm, two-level metal CMOS, and employ Actel’s PLICE® antifuse technology. This revolutionary

architecture offers gate array design flexibility, high performance, and fast time-to-production with user

programming. The ACT 2 family is supported by the Designer and Designer Advantage Systems, which

offers automatic pin assignment, validation of electrical and design rules, automatic placement and

routing, timing analysis, user programming, and diagnostic probe capabilities. The systems are

supported on the following platforms: 386/486™ PC, Sun™, and HP™ workstations. The systems

provide CAE interfaces to the following design environments: Cadence, Viewlogic^®, Mentor Graphics ,

and OrCAD™.

Revision 8

1-1

1 2 3 456 7 8...54

下载PDF