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74LVT18512DGGRE4 PDF预览

74LVT18512DGGRE4

更新时间： 2024-02-19 07:40:23
品牌 Logo 应用领域
德州仪器 - TI 总线收发器微控制器和处理器外围集成电路uCs集成电路uPs集成电路测试光电二极管
页数 文件大小 规格书
36页 585K
描述
3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS

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74LVT18512DGGRE4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP,针数：64
Reach Compliance Code：unknownHTS代码：8542.31.00.01
风险等级：5.84JESD-30 代码：R-PDSO-G64
JESD-609代码：e4长度：17 mm
湿度敏感等级：1端子数量：64
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：1.2 mm最大供电电压：3.6 V
最小供电电压：2.7 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：6.1 mmuPs/uCs/外围集成电路类型：MICROPROCESSOR CIRCUIT
Base Number Matches：1

74LVT18512DGGRE4 数据手册

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SN54LVT18512, SN54LVT182512, SN74LVT18512, SN74LVT182512  
3.3-V ABT SCAN TEST DEVICES  
WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS  
SCBS711 – OCTOBER 1997  
SN54LVT18512, SN54LVT182512 . . . HKC PACKAGE  
SN74LVT18512, SN74LVT182512 . . . DGG PACKAGE  
(TOP VIEW)  
Members of the Texas Instruments  
SCOPE Family of Testability Products  
Members of the Texas Instruments  
Widebus Family  
1CLKAB  
1LEAB  
1OEAB  
1A1  
1CLKBA  
1LEBA  
1OEBA  
1B1  
1B2  
GND  
1B3  
1
64  
63  
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State-of-the-Art 3.3-V ABT Design Supports  
Mixed-Mode Signal Operation (5-V Input  
2
3
and Output Voltages With 3.3-V V  
)
CC  
4
Support Unregulated Battery Operation  
Down to 2.7 V  
1A2  
GND  
1A3  
1A4  
1A5  
5
6
7
UBT (Universal Bus Transceiver)  
Combines D-Type Latches and D-Type  
Flip-Flops for Operation in Transparent,  
Latched, or Clocked Mode  
1B4  
1B5  
8
9
V
V
10  
11  
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CC  
CC  
1A6  
1A7  
1A8  
GND  
1A9  
2A1  
2A2  
2A3  
GND  
2A4  
2A5  
2A6  
1B6  
1B7  
1B8  
GND  
1B9  
2B1  
2B2  
2B3  
GND  
2B4  
2B5  
2B6  
B-Port Outputs of ’LVT182512 Devices  
Have Equivalent 25-Ω Series Resistors, So  
No External Resistors Are Required  
Compatible With the IEEE Std 1149.1-1990  
(JTAG) Test Access Port and  
Boundary-Scan Architecture  
SCOPE Instruction Set  
– IEEE Std 1149.1-1990 Required  
Instructions and Optional CLAMP and  
HIGHZ  
– Parallel-Signature Analysis at Inputs  
– Pseudo-Random Pattern Generation  
From Outputs  
– Sample Inputs/Toggle Outputs  
– Binary Count From Outputs  
– Device Identification  
V
V
CC  
CC  
2A7  
2A8  
2A9  
GND  
2B7  
2B8  
2B9  
GND  
2OEBA  
2LEBA  
2CLKBA  
TDI  
– Even-Parity Opcodes  
2OEAB  
2LEAB  
2CLKAB  
TDO  
Package Options Include 64-Pin Plastic  
Thin Shrink Small Outline (DGG) and 64-Pin  
Ceramic Dual Flat (HKC) Packages Using  
0.5-mm Center-to-Center Spacings  
TMS  
TCK  
description  
The ’LVT18512 and ’LVT182512 scan test devices with 18-bit universal bus transceivers are members of the  
Texas Instruments SCOPE testability integrated-circuit family. This family of devices supports IEEE Std  
1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test  
circuitry is accomplished via the 4-wire test access port (TAP) interface.  
Additionally, these devices are designed specifically for low-voltage (3.3-V) V  
capability to provide a TTL interface to a 5-V system environment.  
operation, but with the  
CC  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
SCOPE, Widebus, and UBT are trademarks of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...36

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