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9FG1201HFLFT

更新时间： 2024-02-24 04:49:34

品牌	Logo	应用领域
艾迪悌 - IDT		PC 时钟
页数	文件大小	规格书
23页	241K
描述
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD

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9FG1201HFLFT 数据手册

DATASHEET

ICS9FG1201H

Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, &

FBD

Description

Features/Benefits

The ICS9FG1201H follows the Intel DB1200G Rev 1.0 Differential

Buffer Specification. This buffer provides 12 output clocks for CPU

Host Bus, PCI-Express, or Fully Buffered DIMM applications. The

outputs are configured with two groups. Both groups (DIF 9:0) and

(DIF 11:10) can be equal to or have a gear ratio to the input clock. A

differential CPU clock from a CK410B or CK410B+ main clock

generator, such as the ICS932S421, drives the ICS9FG1201. The

ICS9FG1201H can provide outputs up to 400MHz

•

Drives 2 channels of 4 FBDIMMs (total of 8 FBDIMMs)

Power up default is all outputs in 1:1 mode

DIF_(9:0) can be “gear-shifted” from the input CPU Host

Clock

•

DIF_(11:10) can be “gear-shifted” from the input CPU Host

Clock

•

Spread spectrum compatible

Supports output clock frequencies up to 400 MHz

8 Selectable SMBus addresses

SMBus address determines PLL or Bypass mode

Key Specifications

•

DIF output cycle-to-cycle jitter < 50ps

DIF output-to-output skew < 50ps within a group

DIF output-to-output skew < 100ps across all outputs

56-pin SSOP/TSSOP package

RoHScompliantpackaging

Functional Block Diagram

OE#

SPREAD

COMPATIBLE

PLL

GEAR

SHIFT

LOGIC

STOP

DIF(11:10)

LOGIC

OE(9:0)#

SPREAD

COMPATIBLE

PLL

GEAR

SHIFT

LOGIC

CLK_IN

STOP

DIF(9:0)

LOGIC

CLK_IN#

HIGH_BW#

FS_A_410

VTT_PWRGD#/PD

SMB_A0

SMB_A1

CONTROL

LOGIC

SMB_A2_PLLBYP#

SMBDAT

SMBCLK

IREF

IDT^TM/ICS^TMFrequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD

1371F — 09/23/09

12 3 4 5 6 7...23

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