Datasheet > 存储 > SRAM> GS8330DW72C-250I

GS8330DW72C-250I

更新时间： 2024-01-07 12:19:55

品牌	Logo	应用领域
GSI		存储内存集成电路静态存储器
页数	文件大小	规格书
30页	583K
描述
Double Late Write SigmaRAM

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GS8330DW72C-250I 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	BGA,	针数：	209
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.B
HTS代码：	8542.32.00.41	风险等级：	5.92
最长访问时间：	2.1 ns	其他特性：	PIPELINED ARCHITECTURE
JESD-30 代码：	R-PBGA-B209	长度：	22 mm
内存密度：	37748736 bit	内存集成电路类型：	STANDARD SRAM
内存宽度：	72	湿度敏感等级：	3
功能数量：	1	端子数量：	209
字数：	524288 words	字数代码：	512000
工作模式：	SYNCHRONOUS	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	512KX72
封装主体材料：	PLASTIC/EPOXY	封装代码：	BGA
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	Not Qualified	最大供电电压 (Vsup)：	1.95 V
最小供电电压 (Vsup)：	1.7 V	标称供电电压 (Vsup)：	1.8 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	14 mm
Base Number Matches：	1

GS8330DW72C-250I 数据手册

Preliminary

GS8330DW36/72C-250/200

209-Bump BGA

Commercial Temp

Industrial Temp

200 MHz–250 MHz

36Mb Σ1x1Dp CMOS I/O

Double Late Write SigmaRAM™

1.8 V V

1.8 V I/O

Features

• Double Late Write mode, Pipelined Read mode

• JEDEC-standard SigmaRAM™ pinout and package

• 1.8 V +150/–100 mV core power supply

• 1.8 V CMOS Interface

• ZQ controlled user-selectable output drive strength

• Dual Cycle Deselect

• Burst Read and Write option

• Fully coherent read and write pipelines

• Echo Clock outputs track data output drivers

• Byte write operation (9-bit bytes)

• 2 user-programmable chip enable inputs

• IEEE 1149.1 JTAG-compliant Serial Boundary Scan

• 209-bump, 14 mm x 22 mm, 1 mm bump pitch BGA package

• Pin-compatible with future 72Mb and 144Mb devices

Bottom View

209-Bump, 14 mm x 22 mm BGA

1 mm Bump Pitch, 11 x 19 Bump Array

Key Fast Bin Specs

Cycle Time

Symbol

tKHKH

tKHQV

-250

4.0 ns

2.1 ns

Access Time

Functional Description

Because SigmaRAMs are synchronous devices, address data

inputs and read/write control inputs are captured on the rising

edge of the input clock. Write cycles are internally self-timed

and initiated by the rising edge of the clock input. This feature

eliminates complex off-chip write pulse generation required by

asynchronous SRAMs and simplifies input signal timing.

ΣRAMs support pipelined reads utilizing a rising-edge-

triggered output register. They also utilize a Dual Cycle

Deselect (DCD) output deselect protocol.

SigmaRAM Family Overview

GS8330DW36/72 SigmaRAMs are built in compliance with

the SigmaRAM pinout standard for synchronous SRAMs.

They are 37,748,736-bit (36Mb) SRAMs. This family of wide,

very low voltage CMOS I/O SRAMs is designed to operate at

the speeds needed to implement economical high performance

networking systems.

ΣRAMs are offered in a number of configurations including

Late Write, Double Late Write, and Double Data Rate (DDR).

The logical differences between the protocols employed by

these RAMs mainly involve various approaches to write

cueing and data transfer rates. The ΣRAM™ family standard

allows a user to implement the interface protocol best suited to

the task at hand.

ΣRAMs are implemented with high performance CMOS

technology and are packaged in a 209-bump BGA.

Rev: 1.00 6/2003

1/30

Specifications cited are design targets and are subject to change without notice. For latest documentation contact your GSI representative.

12 3 4 5 6 7...30

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与GS8330DW72C-250I相关器件

型号	品牌	描述	获取价格	数据表
GS8330DW72C-250IT	GSI	Standard SRAM, 512KX72, 2.1ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209	获取价格
GS8330DW72GC-200	GSI	Standard SRAM, 512KX72, 2.25ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209	获取价格
GS8330DW72GC-200T	GSI	Standard SRAM, 512KX72, 2.25ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209	获取价格
GS8330DW72GC-250IT	GSI	Standard SRAM, 512KX72, 2.1ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209	获取价格
GS8330DW72GC-250T	GSI	Standard SRAM, 512KX72, 2.1ns, CMOS, PBGA209, 14 X 22 MM, 1 MM PITCH, BGA-209	获取价格
GS8330LW36C	GSI	36Mb ヒ1x1Lp CMOS I/O Late Write SigmaRAM	获取价格

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