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9LPRS545CFLFT

更新时间： 2024-02-22 11:53:04
品牌 Logo 应用领域
艾迪悌 - IDT 光电二极管外围集成电路
页数 文件大小 规格书
17页 215K
描述
Microprocessor Circuit, PDSO48, 0.300 INCH, MO-118, SSOP-48

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9LPRS545CFLFT 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SSOP
包装说明：0.300 INCH, MO-118, SSOP-48针数：48
Reach Compliance Code：compliantHTS代码：8542.31.00.01
风险等级：5.63JESD-30 代码：R-PDSO-G48
JESD-609代码：e3长度：15.875 mm
端子数量：48最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：2.8 mm
最大供电电压：3.465 V最小供电电压：3.135 V
标称供电电压：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：MATTE TIN端子形式：GULL WING
端子节距：0.635 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：7.5 mm
uPs/uCs/外围集成电路类型：MICROPROCESSOR CIRCUITBase Number Matches：1

9LPRS545CFLFT 数据手册

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Integrated  
Circuit  
Systems, Inc.  
ICS9LPRS545  
Datasheet  
Absolute Maximum Ratings - DC Parameters  
PARAMETER  
SYMBOL  
VDDxxx  
VDDxxx_IO  
VIH  
CONDITIONS  
Supply Voltage  
MIN  
MAX  
4.6  
UNITS Notes  
Maximum Supply Voltage  
Maximum Supply Voltage  
Maximum Input Voltage  
V
V
V
7
7
Low-Voltage Differential I/O Supply  
3.3V Inputs  
3.8  
4.6  
4,5,7  
Minimum Input Voltage  
Storage Temperature  
Input ESD protection  
VIL  
Ts  
Any Input  
GND - 0.5  
-65  
V
°C  
4,7  
4,7  
6,7  
-
150  
ESD prot  
Human Body Model  
2000  
V
1Guaranteed by design and characterization, not 100% tested in production.  
2 Operation under these conditions is neither implied, nor guaranteed.  
3 Maximum input voltage is not to exceed VDD  
AC Electrical Characteristics - Low Power Differential Outputs  
PARAMETER  
Rising Edge Slew Rate  
Falling Edge Slew Rate  
Slew Rate Variation  
Differential Voltage Swing  
Crossing Point Voltage  
Crossing Point Variation  
Maximum Output Voltage  
Minimum Output Voltage  
Duty Cycle  
SYMBOL  
tSLR  
CONDITIONS  
Averaging on  
MIN  
2.5  
MAX  
4
UNITS NOTES  
V/ns  
V/ns  
%
2, 3  
2, 3  
1, 10  
2
tFLR  
Averaging on  
2.5  
4
tSLVAR  
Averaging on  
20  
VSWING  
VXABS  
Averaging off  
300  
300  
mV  
mV  
mV  
mV  
mV  
%
Averaging off  
550  
140  
1,4,5  
1,4,9  
1,7  
VXABSVAR  
VHIGH  
Averaging off  
Averaging off  
1150  
VLOW  
Averaging off  
-300  
45  
1,8  
DCYC  
Averaging on  
55  
100  
150  
3000  
2
CPU[1:0] Skew  
CPUSKEW10  
CPUSKEW20  
SRCSKEW  
Differential Measurement  
Differential Measurement  
Differential Measurement  
ps  
1
CPU[2_ITP:0] Skew  
SRC[10:0] Skew  
ps  
1
ps  
1,6,11  
NOTES on DIF Output AC Specs: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).  
1Measurement taken for single ended waveform on a component test board (not in system)  
2 Measurement taken from differential waveform on a component test board. (not in system)  
3 Slew rate emastured through V_swing voltage range centered about differential zero  
4 Vcross is defined at the voltage where Clock = Clock#, measured on a component test board (not in system)  
5 Only applies to the differential rising edge (Clock rising, Clock# falling)  
6 Total distributed intentional SRC to SRC skew. PCIE Gen2 outputs (SRC3, 4, 6 and 7) will have 0 nominal skew. Maximum allowable interpair skew is 150 ps.  
7 The max voltage including overshoot.  
8 The min voltage including undershoot.  
9 The total variation of all Vcross measurements in any particular system. Note this is a subset of V_cross min/mas (V_Cross absolute) allowed. The intent is to limit Vcross  
10 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising  
11 For PCIe Gen2 compliant devices, SRC 3, 4, 6, and 7 will have 0 ps nominal skew.  
Electrical Characteristics - PCICLK/PCICLK_F  
PARAMETER  
SYMBOL  
CONDITIONS  
see Tperiod min-max values  
33.33MHz output no spread  
33.33MHz output spread  
33.33MHz output no spread  
33.33MHz output nominal/spread  
IOH = -1 mA  
MIN  
MAX  
UNITS NOTES  
Long Accuracy  
ppm  
-100  
100  
ppm  
ns  
ns  
ns  
ns  
V
1,2  
2
29.99700 30.00300  
30.08421 30.23459  
29.49700 30.50300  
29.56617 30.58421  
2.4  
Clock period  
Tperiod  
Tabs  
2
2
Absolute min/max period  
2
Output High Voltage  
Output Low Voltage  
VOH  
VOL  
1
IOL = 1 mA  
0.55  
V
mA  
mA  
mA  
mA  
V/ns  
V/ns  
ps  
1
1
1
1
1
1
1
2
2
2
2
V
OH @MIN = 1.0 V  
VOH@MAX = 3.135 V  
OL @ MIN = 1.95 V  
-33  
-33  
30  
Output High Current  
Output Low Current  
IOH  
IOL  
V
VOL @ MAX = 0.4 V  
Measured from 0.8 to 2.0 V  
Measured from 2.0 to 0.8 V  
VT = 1.5 V  
38  
Rising Edge Slew Rate  
Falling Edge Slew Rate  
Pin to Pin Skew  
tSLR  
tFLR  
1
1
4
4
tskew  
tskew  
dt1  
250  
200  
55  
Intential PCI to PCI delay  
Duty Cycle  
VT = 1.5 V  
100  
45  
ps  
VT = 1.5 V  
%
Jitter, Cycle to cycle  
tjcyc-cyc  
VT = 1.5 V  
500  
ps  
1479A—07/28/09  
5
12345678...17

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