5秒后页面跳转
捷配首页

Datasheet > 微控制器和处理器 > 其他 uPs/uCs/外围集成电路> 9LPRS525AGILF
9LPRS525AGILF PDF预览

9LPRS525AGILF

更新时间： 2024-01-25 03:14:39
品牌 Logo 应用领域
艾迪悌 - IDT /
页数 文件大小 规格书
21页 235K
描述
TSSOP-56, Tube

阅读下载

获取价格

9LPRS525AGILF 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：TSSOP
包装说明：6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-56针数：56
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：1.3
Samacsys Confidence：3Samacsys Status：Released
2D Presentation：https://componentsearchengine.com/2D/0T/1284768.2.1.pngSchematic Symbol：https://componentsearchengine.com/symbol.php?partID=1284768
PCB Footprint：https://componentsearchengine.com/footprint.php?partID=12847683D View：https://componentsearchengine.com/viewer/3D.php?partID=1284768
Samacsys PartID：1284768Samacsys Image：https://componentsearchengine.com/Images/9/9LPRS525AGLF.jpg
Samacsys Thumbnail Image：https://componentsearchengine.com/Thumbnails/2/9LPRS525AGLF.jpgSamacsys Pin Count：56
Samacsys Part Category：Integrated CircuitSamacsys Package Category：Small Outline Packages
Samacsys Footprint Name：PAG56_Samacsys Released Date：2020-01-17 12:09:31
Is Samacsys：NJESD-30 代码：R-PDSO-G56
JESD-609代码：e3长度：14 mm
湿度敏感等级：1端子数量：56
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP56,.3,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：3.3 V认证状态：Not Qualified
座面最大高度：1.2 mm子类别：Clock Generators
最大压摆率：200 mA最大供电电压：3.465 V
最小供电电压：3.135 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Matte Tin (Sn) - annealed
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
宽度：6.1 mmuPs/uCs/外围集成电路类型：MICROPROCESSOR CIRCUIT
Base Number Matches：1

9LPRS525AGILF 数据手册

 浏览型号9LPRS525AGILF的Datasheet PDF文件第3页浏览型号9LPRS525AGILF的Datasheet PDF文件第4页浏览型号9LPRS525AGILF的Datasheet PDF文件第5页浏览型号9LPRS525AGILF的Datasheet PDF文件第7页浏览型号9LPRS525AGILF的Datasheet PDF文件第8页浏览型号9LPRS525AGILF的Datasheet PDF文件第9页 
ICS9LPRS525  
PC MAIN CLOCK  
NOTES on Input/Supply/Common Output DC Parameters: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).  
1Signal is required to be monotonic in this region.  
2 input leakage current does not include inputs with pull-up or pull-down resistors  
3 3.3V referenced inputs are: PCI_STOP#, CPU_STOP#, TME, SRC5_EN, ITP_EN, SCLKL, SDATA, TESTMODE, TESTSEL, CKPWRGD and CR# inputs if selected.  
4 Intentionally blank  
5 Maximum VIH is not to exceed VDD  
6 Human Body Model  
7 Operation under these conditions is neither implied, nor guaranteed.  
8 Frequency Select pins which have tri-level input  
9 PCI3/CFG0 is optional  
10 If present. Not all parts have this feature.  
AC Electrical Characteristics - Low Power Differential Outputs  
PARAMETER  
Rising Edge Slew Rate  
Falling Edge Slew Rate  
Slew Rate Variation  
Differential Voltage Swing  
Crossing Point Voltage  
Crossing Point Variation  
Maximum Output Voltage  
Minimum Output Voltage  
Duty Cycle  
SYMBOL  
tSLR  
tFLR  
tSLVAR  
VSWING  
VXABS  
CONDITIONS  
Averaging on  
Averaging on  
Averaging on  
Averaging off  
Averaging off  
Averaging off  
Averaging off  
Averaging off  
MIN  
2.5  
2.5  
MAX  
4
4
UNITS NOTES  
V/ns  
V/ns  
%
mV  
mV  
mV  
mV  
mV  
%
2, 3  
2, 3  
1, 10  
2
1,4,5  
1,4,9  
1,7  
1,8  
2
20  
300  
300  
550  
140  
1150  
VXABSVAR  
VHIGH  
VLOW  
DCYC  
CPUSKEW10  
CPUSKEW20  
SRCSKEW  
-300  
45  
Averaging on  
55  
100  
150  
3000  
CPU[1:0] Skew  
CPU[2_ITP:0] Skew  
SRC[10:0] Skew  
Differential Measurement  
Differential Measurement  
Differential Measurement  
ps  
1
ps  
1
ps  
1,6,11  
NOTES on DIF Output AC Specs: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).  
1Measurement taken for single ended waveform on a component test board (not in system)  
2 Measurement taken from differential waveform on a component test board. (not in system)  
3 Slew rate emastured through V_swing voltage range centered about differential zero  
4 Vcross is defined at the voltage where Clock = Clock#, measured on a component test board (not in system)  
5 Only applies to the differential rising edge (Clock rising, Clock# falling)  
6 Total distributed intentional SRC to SRC skew. PCIE Gen2 outputs (SRC3, 4, 6 and 7) will have 0 nominal skew. Maximum allowable interpair skew is 150 ps.  
7 The max voltage including overshoot.  
8 The min voltage including undershoot.  
9 The total variation of all Vcross measurements in any particular system. Note this is a subset of V_cross min/mas (V_Cross absolute) allowed. The intent is to limit Vcross induced  
modulation by setting C_cross_delta to be smaller than V_Cross absolute  
10 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising meets  
Clock# falling. The median cross point is used to calculate the voltage  
11 For PCIe Gen2 compliant devices, SRC 3, 4, 6, and 7 will have 0 ps nominal skew.  
Clock Jitter Specs - Low Power Differential Outputs  
PARAMETER  
SYMBOL  
CPUJC2C  
SRCJC2C  
DOTJC2C  
CONDITIONS  
MIN  
MAX  
85  
125  
250  
UNITS NOTES  
CPU Jitter - Cycle to Cycle  
SRC Jitter - Cycle to Cycle  
DOT Jitter - Cycle to Cycle  
Differential Measurement  
Differential Measurement  
Differential Measurement  
ps  
ps  
ps  
1
1,2  
1
NOTES on DIF Output Jitter: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).  
1JItter specs are specified as measured on a clock characterization board. System designers need to take special care not to use these numbers, as the in-system performance will be  
somewhat degraded. The receiver EMTS (chispet or CPU) will have the rece  
2
Phase jitter requirement: The deisgnated Ge2 outputs will meet the reference clock jitter requiremernts from the PCI Express Gen2 Base Spec. The test is performed on a componnet  
test board under quiet condittions with all outputs on. Jitter analysis is performed using a standardized tool provided by the PCI SIG or equivalent. Measurement methodology is as defined  
by the PCI SIG.  
IDTTM/ICSTM PC MAIN CLOCK  
1484A—04/28/09  
6
1...3456789...21

下载PDF

与9LPRS525AGILF相关器件

型号 品牌 描述 获取价格 数据表
9LPRS525AGLF IDT TSSOP-56, Tube

获取价格
9LPRS525AGLFT IDT 56-pin CK505 for Intel Systems

获取价格
9LPRS535 IDT 48-pin CK505 for Intel Systems

获取价格
9LPRS535BFLF IDT 48-pin CK505 for Intel Systems

获取价格
9LPRS535BFLFT IDT 48-pin CK505 for Intel Systems

获取价格
9LPRS535BGLF IDT 48-pin CK505 for Intel Systems

获取价格

与9LPRS525AGILF相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证