ICS9ERS3165
Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
TSSOP Pin Description (Continued)
TYPE
PIN #
PIN NAME
DESCRIPTION
SRC11 true or Clock Request control H for SRC10 pair
The power-up default is SRC11, but this pin may also be used as a Clock Request
control of SRC10 via SMBus. Before configuring this pin as a Clock Request Pin, the
SRC11 output pair must first be disabled in byte 3, bit 7 of SMBus configuration
33 SRCT_LR11/CR#_H
I/O space After the SRC11 output is disabled (high-Z), the pin can then be set to serve
as a Clock Request for SRC10 pair using byte 6, bit 4 of SMBus configuration space
Byte 6, bit 4
0 = SRC11 enabled (default)
1= CR#_H controls SRC10.
34 SRCT_LR10
35 SRCC_LR10
36 VDDSRCI/O
OUT True clock of differential SRC clock pair.
OUT Complement clock of differential SRC clock pair.
PWR 1.05V to 3.3V from external power supply
Stops all CPU Clocks, except those set to be free running clocks. In AMT mode 3
37 CPU_STOP#
38 PCI_STOP#
IN
bits are shifted in from the ICH to set the FSC, FSB, FSA values
Stops all PCI Clocks, except those set to be free running clocks. In AMT mode 3 bits
IN
are shifted in from the ICH to set the FSC, FSB, FSA values
39 VDDSRC
40 SRCC_LR6
41 SRCT_LR6
42 GNDSRC
PWR VDD pin for SRC Pre-drivers, 3.3V nominal
OUT Complement clock of low power differential SRC clock pair.
OUT True clock of low power differential SRC clock pair.
PWR Ground for SRC clocks
SRC7 complement or Clock Request control E for SRC6 pair
The power-up default is SRC7#, but this pin may also be used as a Clock Request
control of SRC6 via SMBus. Before configuring this pin as a Clock Request Pin, the
SRC7 output pair must first be disabled in byte 3, bit 3 of SMBus configuration space
I/O . After the SRC output is disabled (high-Z), the pin can then be set to serve as a
Clock Request for SRC6 pair using byte 6, bit 7 of SMBus configuration space
Byte 6, bit 7
43 SRCC_LR7/CR#_E
0 = SRC7# enabled (default)
1= CR#_E controls SRC6.
SRC7 true or Clock Request control 8 for SRC8 pair
The power-up default is SRC7, but this pin may also be used as a Clock Request
control of SRC8 via SMBus. Before configuring this pin as a Clock Request Pin, the
SRC7 output pair must first be disabled in byte 3, bit 3 of SMBus configuration space
I/O After the SRC output is disabled (high-Z), the pin can then be set to serve as a Clock
Request for SRC8 pair using byte 6, bit 6 of SMBus configuration space
Byte 6, bit 6
44 SRCT_LR7/CR#_F
0 = SRC7# enabled (default)
1 = CR#_F controls SRC8.
45 VDDSRCI/O
PWR 1.05V to 3.3V from external power supply
Complement clock of low power differential CPU2/Complement clock of differential
SRC pair. The function of this pin is determined by the latched input value on pin 7,
PCIF5/ITP_EN on powerup. The function is as follows:
46 CPUC_ITP_LR2/SRCC8
OUT
Pin 7 latched input Value
0 = SRC8#
1 = ITP#
True clock of low power differential CPU2/True clock of differential SRC pair. The
function of this pin is determined by the latched input value on pin 7, PCIF5/ITP_EN
on powerup. The function is as follows:
47 CPUT_ITP_LR2/SRCT8
OUT
Pin 7 latched input Value
0 = SRC8
1 = ITP
N/A No Connect
48 NC
49 VDDCPU_IO
PWR 1.05V to 3.3V from external power supply
Complement clock of low power differenatial CPU clock pair. This clock will be free-
50 CPUC_F_LR1
51 CPUT_F_LR1
OUT
running during iAMT.
True clock of low power differential CPU clock pair. This clock will be free-running
OUT
during iAMT.
52 GNDCPU
53 CPUC_LR0
54 CPUT_LR0
55 VDDCPU
PWR Ground Pin for CPU Outputs
OUT Complement clock of low power differential CPU clock pair.
OUT True clock of low power differential CPU clock pair.
PWR Power Supply 3.3V nominal.
56 CK_PWRGD/PD#
IN Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time input to
57 FSLB/TEST_MODE
IN
select between Hi-Z and REF/N divider mode while in test mode. Refer to Test
Clarification Table.
PWR Ground pin for crystal oscillator circuit
OUT Crystal output, nominally 14.318MHz.
58 GNDREF
59 X2
60 X1
IN Crystal input, Nominally 14.318MHz.
61 VDDREF
PWR Power pin for the REF outputs, 3.3V nominal.
3.3V 14.318MHz reference clock/3.3V tolerant low threshold input for CPU frequency
selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values/
62 REF/FSLC/TEST_SEL
I/O
TEST_SEL: 3-level latched input to enable test mode. Refer to Test Clarification
Table.
I/O Data pin for SMBus circuitry, 5V tolerant.
IN Clock pin of SMBus circuitry, 5V tolerant.
63 SDATA
64 SCLK
IDT® Embedded 64-Pin Industrial Temperature Range CK505 Compatible Clock
1613C—02/08/12
4
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