Datasheet > 9DML0441

9DML0441

更新时间： 2022-02-26 11:13:26

品牌	Logo	应用领域
艾迪悌 - IDT		PC
页数	文件大小	规格书
10页	238K
描述
2:4 3.3V PCIe Clock Mux

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9DML0441 数据手册

2:4 3.3V PCIe Clock Mux

9DML0441 / 9DML0451

DATASHEET

Description

Features

The 9DML0441 / 9DML0451 devices are 3.3V members of

IDT's Full-Featured PCIe family. They support PCIe Gen1-4

Common Clocked (CC), Separate Reference no Spread

(SRnS), and Separate Reference Independent Spread

(SRIS) architectures. The parts provide a choice of

asynchronous and glitch-free switching modes, and offer a

choice of integrated output terminations for direct connection

to 85 or 100 transmission lines. The 9DML04P1 can be

factory programmed with a user-defined power-up default

configuration.

• Direct connection to 100 (xx41) or 85 (xx51)

transmission lines saves up to 16 resistors

• 79mW typical power consumption

• Spread Spectrum (SS) compatible

• Factory programmed P1 device allows exact optimization

to customer requirements:

• Control input polarity

• Control input pull up/downs

• Slew rate for each output

• Differential output amplitude

• Output impedance for each output

• OE# pins for each output

Typical Applications

Servers, ATCA, ATE, Storage, Master/Slave applications

• HCSL-compatible differential inputs; can be driven by

common clock source

Output Features

• Four 1–200MHz Low-Power HCSL (LP-HCSL) DIF pairs

• 9DML0441 default ZOUT = 100

• Selectable asynchronous or glitch-free switching; allows

the mux to be selected at power-up even if both inputs are

not running, then transition to glitch-free switching mode

• 9DML0451 default ZOUT = 85

• Space saving 4 × 4 mm 24-VFQFPN

• 9DML04P1 factory programmable defaults

• See AN-891 for easy termination to other logic levels

Key Specifications

• PCIe Gen1–4 CC compliant

• PCIe Gen2–3 SRIS compliant

• Output-to-output skew < 50ps

• PCIe Gen4 additive phase jitter is < 0.1 ps rms

• 12kHz–20MHz additive phase jitter 285fs rms typical

at156.25MHz

Block Diagram

VDDR3.3 x2

VDD3.3

^OE(3:0)#

DIF3#

DIF3

DIF2#

DIF_INA#

DIF_INA

DIF2

DIF1#

DIF1

DIF0#

DIF0

DIF_INB#

DIF_INB

vSW_MODE

^SEL_A_B#

EPAD/GND

GNDR x2

GND

Note: Resistors default to internal on xx41/xx51 devices. P1 devices have programmable default impedances on an output-by-output basis.

9DML0441 / 9DML0451 AUGUST 27, 2018

12 3 4 5 6 7...10

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