9DBL411AKLFT

更新时间： 2024-01-21 10:59:45

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艾迪悌 - IDT		PC
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9页	85K
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9DBL411AKLFT 数据手册

9DBL411B

Four Output Low Power Differential Buffer for PCI Express Gen1, Gen2, and QPI

Advance Information

AC Electrical Characteristics - DIF Low Power Differential Outputs

PARAMETER

SYMBOL

CONDITIONS

MIN

MAX

UNITS

V/ns

NOTES

Rising Edge Slew Rate

Falling Edge Slew Rate

Slew Rate Variation

t_SLR

Differential Measurement

Single-ended Measurement

Includes overshoot

1.5

1,2

t_FLR

1.5

t_SLVAR

V_HIGH

Maximum Output Voltage

Minimum Output Voltage

Differential Voltage Swing

Crossing Point Voltage

Crossing Point Variation

1150

V_LOW

Includes undershoot

-300

1200

300

V_SWING

V_XABS

V_XABSVAR

Differential Measurement

Single-ended Measurement

550

140

1,3,4

1,3,5

Differential Measurement,

fIN<=133.33MHz

Differential Measurement,

Duty Cycle Distortion

D_CYCDIS0

1,6

Additive Cycle to Cycle Jitter

DIFJ_C2CADD

Additive

DIF[3:0] Skew

DIF_SKEW

t_PD

Differential Measurement

Input to output Delay

Propagation Delay

2.5

3.5

Additive Phase Jitter - PCIe

Gen1

Additive Phase Jitter - PCIe

Gen2 High Band

Additive Phase Jitter PCIe

Gen2 Low Band

Additive Phase Jitter QPI133

(6.4GBs, 12 UI)

t_{phase_addPCIG1}

t_{phase_addPCIG2HI}

t_{phase_addPCIG2LO}

t_{phase_addQPI6G4}

1.5MHz < 22MHz

ps Pk-Pk

ps rms

1,9

High Band is 1.5MHz to Nyquist

(50MHz)

0.16

0.07

0.04

Low Band is 10KHz to 1.5MHz

11MHz to 33MHz

Notes on Electrical Characteristics (all measurements use 9LRS3187B as clock source and R_S=33ohms/C_L=2pF test load):

¹Guaranteed by design and characterization, not 100% tested in production.

²Slew rate measured through Vswing centered around differential zero

³Vxabs is defined as the voltage where CLK = CLK#

⁴Only applies to the differential rising edge (CLK rising and CLK# falling)

⁵Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of CLK and

falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets CLK#.

⁶This figure refers to the maximum distortion of the input wave form.

⁷Operation under these conditions is neither implied, nor guaranteed.

⁸Maximum input voltage is not to exceed maximum VDD

⁹The 9DBL411B has no PLL, so the part itself contributes very little jitter to the input clock. But this also means that the 9DBL411

cannot 'de-jitter' a noisy input clock. Values calculated per PCI SIG and per Intel Clock Jitter tool version 1.5

IDT^®Four Output Low Power Differential Buffer for PCI Express for Gen1, Gen2, and QPI

1645C—10/18/10

1...3 4 567 8 9

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与9DBL411AKLFT相关器件

型号	品牌	获取价格	描述	数据表
9DBL411B	IDT	获取价格	Four Output Low Power Differential Fanout Buffer for PCI Express Gen1, Gen2, and QPI
9DBL411BGILF	IDT	获取价格	Four Output Low Power Differential Fanout Buffer for PCI Express Gen1, Gen2, and QPI
9DBL411BGILFT	IDT	获取价格	Four Output Low Power Differential Fanout Buffer for PCI Express Gen1, Gen2, and QPI
9DBL411BGLF	IDT	获取价格	Four Output Low Power Differential Fanout Buffer for PCI Express Gen1, Gen2, and QPI
9DBL411BGLFT	IDT	获取价格	Four Output Low Power Differential Fanout Buffer for PCI Express Gen1, Gen2, and QPI
9DBL411BKILF	IDT	获取价格	Four Output Low Power Differential Fanout Buffer for PCI Express Gen1, Gen2, and QPI
9DBL411BKILFT	IDT	获取价格	Four Output Low Power Differential Fanout Buffer for PCI Express Gen1, Gen2, and QPI
9DBL411BKLF	IDT	获取价格	Four Output Low Power Differential Fanout Buffer for PCI Express Gen1, Gen2, and QPI
9DBL411BKLFT	IDT	获取价格	Four Output Low Power Differential Fanout Buffer for PCI Express Gen1, Gen2, and QPI
9DBU0231	RENESAS	获取价格	2-output 1.5V PCIe Zero-Delay/Fanout Clock Buffer

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