Datasheet > 9DB306LLFT

9DB306LLFT

更新时间： 2024-01-14 14:47:59

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
15页	309K
描述
Clock Driver

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9DB306LLFT 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
包装说明：	,	Reach Compliance Code：	compliant
风险等级：	5.84	Base Number Matches：	1

9DB306LLFT 数据手册

ICS9DB306

Integrated

Circuit

Systems, Inc.

PCI EXPRESS

JITTER

ATTENUATOR

TERMINATION FOR LVPECL OUTPUTS

The clock layout topology shown below is a typical termina-

tion for LVPECL outputs.The two different layouts mentioned

are recommended only as guidelines.

50Ω transmission lines. Matched impedance techniques should

be used to maximize operating frequency and minimize signal

distortion. Figures 3A and 3B show two different layouts which

are recommended only as guidelines. Other suitable clock lay-

outs may exist and it would be recommended that the board

designers simulate to guarantee compatibility across all printed

circuit and clock component process variations.

FOUT and nFOUT are low impedance follower outputs that gen-

erate ECL/LVPECL compatible outputs.Therefore, terminating

resistors (DC current path to ground) or current sources must

be used for functionality. These outputs are designed to drive

3.3V

_o= 50Ω

125Ω

FOUT

FIN

Z_o= 50Ω

FOUT

FIN

50Ω

V_CC- 2V

RTT =

Z_o

RTT

((V_OH+ V_OL) / (V_CC– 2)) – 2

84Ω

FIGURE 3A. LVPECL OUTPUT TERMINATION

FIGURE 3B. LVPECL OUTPUT TERMINATION

9DB306BL

www.icst.com/products/hiperclocks.html

REV. A OCTOBER 22, 2004

1...5 6 789 10 11...15

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