Integrated
Circuit
ICS952906A
Systems, Inc.
Programmable Timing Control Hub™ for Next Gen P4™ processor
Recommended Application:
Features/Benefits:
VIA VN800/CN700/P4M800 style chipset for P4 processor
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•
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•
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Programmable output frequency.
Programmable asynchronous 3V66&PCI frequency.
Programmable output divider ratios.
Programmable output skew.
Programmable spread percentage for EMI control.
Watchdog timer technology to reset system if system
malfunctions.
Programmable watch dog safe frequency.
Support I2C Index read/write and block read/write
operations.
Uses external 14.318MHz reference input.
Output Features:
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3 - 0.7V current-mode differential CPU pairs
10 - PCI, 3 free running, 33MHz
2 - REF, 14.318MHz
3 - 3V66, 66.66MHz
1 - 48MHz
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1 - 24/48MHz
2 - 25MHz @ 2.5V
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Key Specifications:
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CPU/SRC outputs cycle-cycle jitter < 125ps
3V66 outputs cycle-cycle jitter < 250ps
PCI outputs cycle-cycle jitter < 250ps
CPU - AGP skew < +/- 350ps
AGP-PCI skew between 1~3.5ns
Functionality
Pin Configuration
Bit4 Bit3 Bit2 Bit1 Bit0 CPU
FS4 FS3 FS2 FS1 FS0 MHz
AGP
MHz
PCI
MHz
33.33
*FS1/REF0
**FS0/REF1
VDDREF
1
48 VDDA
47 GND
46 IREF
45 CPUCLKT_ITP/(PCI_STOP#)
44 CPUCLKC_ITP/(CPU_STOP#)
43 GND
42 CPUCLKT1
41 CPUCLKC1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
100.00 66.67
200.00 66.67
133.33 66.67
166.67 66.67
200.00 66.67
400.00 66.67
266.67 66.67
333.33 66.67
100.99 67.33
201.98 67.33
134.65 67.33
168.31 67.32
115.00 76.67
230.00 76.67
153.33 76.66
191.67 76.67
100.00 66.66
200.00 66.66
133.33 66.66
166.67 71.43
200.00 66.66
400.00 66.66
266.67 66.66
333.33 66.66
105.00 69.99
210.00 69.99
140.00 69.99
175.00 69.99
110.00 73.33
220.00 73.33
146.66 73.33
183.34 73.33
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
X1
X2
GND
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.66
33.66
33.66
33.66
38.33
38.33
38.33
38.33
33.33
33.33
33.33
35.71
33.33
33.33
33.33
33.33
35.00
35.00
35.00
35.00
36.66
36.66
36.66
36.66
**FS2/PCICLK_F0
**FS4/PCICLK_F1
PCICLK_F2
40
VDDCPU
39 CPUCLKT0
38 CPUCLKC0
37
GND
36 25Mhz_0
VDDPCI
GND
**MODE/PCICLK0
PCICLK1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
35 25Mhz_1
PCICLK2
PCICLK3
PCICLK4
VDDPCI
GND
PCICLK5
PCICLK6
34
VDD2.5
33 VttPWR_GD/PD#
32 SDATA
31 SCLK
1
1
1
0
0
0
0
1
30
29
28
Reset#
3V66_0
GND
21
**FS3/48MHz
**Sel24_48#/24_48MHz 22
27 VDD3V66
26
1
1
1
1
1
1
1
1
1
1
1
1
1
23
24
GND
VDD48
3V66_1
25 3V66_2
* This pin have 120K pull-up to VDD
** This pin have 120K pull-down to GND
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
48-pin SSOP & TSSOP
1
1
1
1
1
1
1
1
1
0
1
1236A—08/06/07