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932S825AGT PDF预览

932S825AGT

更新时间: 2024-02-08 12:15:41
品牌 Logo 应用领域
艾迪悌 - IDT 光电二极管
页数 文件大小 规格书
20页 231K
描述
Clock Generator, PDSO64

932S825AGT 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
Reach Compliance Code:unknown风险等级:5.92
JESD-30 代码:R-PDSO-G64端子数量:64
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP64,.32,20封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH电源:3.3 V
认证状态:Not Qualified子类别:Clock Generators
最大压摆率:250 mA标称供电电压:3.3 V
表面贴装:YES温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.5 mm
端子位置:DUALBase Number Matches:1

932S825AGT 数据手册

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ICS932S825  
Pin Description  
PIN #  
PIN NAME  
TYPE  
IN  
DESCRIPTION  
Crystal input, Nominally 14.318MHz.  
1
2
3
X1  
X2  
OUT  
PWR  
Crystal output, Nominally 14.318MHz  
VDDREF_STB  
Ref, XTAL power supply, nominal 3.3V standby power  
14.318MHz Free Running XTAL Output. This output runs as long as  
standby VDD is applied to the part. Default drive is 2 loads.  
Frequency select latch input pin / 14.318 MHz reference clock. Default 2  
load drive.  
4
5
6
REF0_RUN_2x  
FS1/REF1_2x  
FS2/REF2_2x  
OUT  
I/O  
Frequency select latch input pin / 14.318 MHz reference clock. Default 2  
load drive.  
I/O  
7
GNDREF  
VDD48  
PWR  
PWR  
OUT  
OUT  
PWR  
IN  
Ground pin for the REF outputs.  
8
Power pin for the 48MHz output.3.3V  
9
48MHz_0_2x  
48MHz_1_2x  
GND48  
48MHz clock output. Default 2 load drive strength  
48MHz clock output. Default 2 load drive strength  
Ground pin for the 48MHz outputs  
10  
11  
12  
13  
14  
15  
16  
17  
SCLK  
Clock pin of SMBus circuitry, 5V tolerant.  
Data pin for SMBus circuitry, 3.3V tolerant.  
Power supply for PCI clocks, nominal 3.3V  
3.3V PCI clock output. Default 2 load drive strength.  
3.3V PCI clock output. Default 2 load drive strength.  
SDATA  
I/O  
VDDPCI  
PWR  
OUT  
OUT  
PWR  
PCICLK0_2x  
PCICLK1_2x  
GNDPCI  
Ground pin for the PCI outputs  
This 3.3V LVTTL input is a level sensitive strobe used to determine when  
latch inputs are valid and are ready to be sampled. This is an active high  
input. / Asynchronous active low input pin used to power down the device  
into a low power state.  
18  
CLKPWRGD/PD#  
IN  
19  
20  
21  
22  
GND  
PWR  
PWR  
PWR  
PWR  
Ground pin.  
VDDA  
GNDA  
GND  
3.3V power for the PLL core.  
Ground pin for the PLL core.  
Ground pin.  
True clock of 0.8V differential push-pull PCI_Express pair (no 50ohm  
resistor to GND needed)  
Complement clock of 0.8V differential push-pull PCI_Express pair. (no  
50ohm resistor to GND needed)  
True clock of 0.8V differential push-pull PCI_Express pair (no 50ohm  
resistor to GND needed)  
Complement clock of 0.8V differential push-pull PCI_Express pair. (no  
50ohm resistor to GND needed)  
23  
24  
25  
26  
PCIeT_L0  
PCIeC_L0  
PCIeT_L1  
PCIeC_L1  
OUT  
OUT  
OUT  
OUT  
27  
28  
GND  
PWR  
PWR  
Ground pin.  
VDDPCIe  
Power supply for PCI Express clocks, nominal 3.3V  
True clock of 0.8V differential push-pull PCI_Express pair (no 50ohm  
resistor to GND needed)  
Complement clock of 0.8V differential push-pull PCI_Express pair. (no  
50ohm resistor to GND needed)  
True clock of 0.8V differential push-pull PCI_Express pair (no 50ohm  
resistor to GND needed)  
Complement clock of 0.8V differential push-pull PCI_Express pair. (no  
50ohm resistor to GND needed)  
29  
30  
31  
32  
PCIeT_L2  
PCIeC_L2  
PCIeT_L3  
PCIeC_L3  
OUT  
OUT  
OUT  
OUT  
1276E—12/14/07  
2

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