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9176CM-03LF PDF预览

9176CM-03LF

更新时间: 2024-01-20 10:37:50
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
8页 224K
描述
PLL Based Clock Driver, 10 True Output(s), 0 Inverted Output(s), CMOS, PDSO28, 0.300 INCH, MS-013, MO-119, SOIC-28

9176CM-03LF 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP,针数:28
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.57其他特性:ALSO OPERATES AT 5V SUPPLY
输入调节:STANDARDJESD-30 代码:R-PDSO-G28
JESD-609代码:e3长度:18.05 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER功能数量:1
反相输出次数:端子数量:28
实输出次数:10最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):1 ns
座面最大高度:2.65 mm最大供电电压 (Vsup):3.465 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:MATTE TIN
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:7.5 mm最小 fmax:90 MHz
Base Number Matches:1

9176CM-03LF 数据手册

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Integrated  
Circuit  
Systems, Incꢀ  
ICS9176C-03  
Low Skew Output Buffer  
General Description  
Features  
3.3 or 5.0 volt supply operation  
The IC9176C-03 is designed specifically to support the  
tight timing requirements of high-performance  
microprocessors and chip sets. Because the jitter of the  
device is limited to ±250ps, the ICS9176C-03 is ideal for  
clocking Pentium™ systems. the 10 high drive (40mA), low-  
skew (±250ps) outputs make the ICS9176C-03 a perfect fit  
for PCI clocking requirements.  
±500 skew (max) between input and outputs  
±250ps skew (max) between outputs  
10 symmetric, TLL-compatible outputs  
28-pin SOIC package  
High drive, 40mA outputs  
Power-down option  
The ICS9176C-03 has 10 outputs synchronized in phase and  
frequency to an input clock. The internal phase locked loop  
(PLL) acts either as 1X clock multiplier or a 1/2X clock  
multiplier depending on the state of the input control pins T0  
and T1. With metal mask options, any type of ratio between  
the input clock and output clock can be achieved, including  
2X.  
Output frequency range 25 MHz to 120 MHz  
Input frequency range 25 MHz to 100 MHz  
Ideal for PCI bus applications  
Selection Table  
The PLL maintains the phase frequency relationship between  
the input clock and the outputs by externally feeding back  
FBOUT to FBIN. Any change in the input will be tracked by  
all 10 outputs. However, the change at the outputs will  
happen smoothly so no glitches will be present on any driven  
input. The PLL circuitry matches rising edges of the input  
clock and the output clock. Since the input to FBIN skew is  
guarenteed to ±500ps, the part acts as a "zero delay" buffer.  
T1  
0
T0  
0
Description  
Power-down  
0
1
Test Mode (PLL Off CLK=outputs)  
Normal (PLL On)  
Divide by 2 Mode  
1
0
1
1
The ICS9176C-03 has a total of eleven ouputs. Of these,  
FBOUT is dedicated as the feedback into the PLLand another,  
Q/2, has an output frequency half that of the remaining nine.  
These nine outputs can either by running at the same speed as  
the input, or at half the frequency of the input. With Q/2 as  
the feedback to FBIN, the nine 'Q' outputs will be running at  
twice the input frequency in the normal divide-by-1 mode.  
In this case, the output can go to 120 MHz with a 60 MHz  
input clock. The maximum rise and fall time of an output is  
14ns and each is TTL-compatible with a 40mA symmetric  
drive.  
Block Diagram  
The ICS9176C-03 is fabricated using CMOS technology  
which results in much lower power consumption and cost  
compared with the gallium arsenide based 1086E. The typical  
operatingcurrentforthe ICS9176C-03is60mAversus115mA  
for the GA1086E.  
9176C-03RevD01/29/02  
ICS reserves the right to make changes in the device data identified in this  
publication without further notice. ICS advises its customers to obtain the latest  
version of all device data to verify that any information being relied upon by the  
customer is current and accurate.  

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