Datasheet > 9176Q-01

9176Q-01

更新时间： 2024-02-28 01:12:32

品牌	Logo	应用领域
艾迪悌 - IDT		驱动逻辑集成电路
页数	文件大小	规格书
8页	379K
描述
PLL Based Clock Driver, PQCC28, PLASTIC, LCC-28

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9176Q-01 技术参数

生命周期：	Active	零件包装代码：	QLCC
包装说明：	,	针数：	28
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.57	JESD-30 代码：	S-PQCC-J28
逻辑集成电路类型：	PLL BASED CLOCK DRIVER	端子数量：	28
封装主体材料：	PLASTIC/EPOXY	封装形状：	SQUARE
封装形式：	CHIP CARRIER	认证状态：	Not Qualified
表面贴装：	YES	端子形式：	J BEND
端子位置：	QUAD	Base Number Matches：	1

9176Q-01 数据手册

ICS9176-01

Integrated

Circuit

Systems, Inc.

Low Skew Output Buffer

General Description

Features

•

ICS9176-01-01 is pin compatible with Triquint GA1086

±500ps skew (max) between input and outputs

±250ps skew (max) between outputs

10 symmetric, TLL-compatible outputs

28-pin PLCC or 28-pin wide SOIC surface mount

package

the ICS9176-01 is designed specifically to support the tight

timing requirements of high-performance microprocessors

and chip sets. Because the jitter of the device is limited to

±250ps, the ICS9176-01 is ideal for clocking Pentium™

systems. The 10 high drive (40mA), low-skew (±250ps)

outputs make the ICS9176-01 a perfect fit for PCI clocking

requirements.

•

High drive, 40mA outputs

Power-down option

Output frequency range 20 MHz to 120 MHz

Input frequency range 20 MHz to 100 MHz

Ideal for PCI bus applications

The ICS9176-01 has 10 outputs synchronized in phase and

fre-quency to an input clock. The internal phase locked loop

(PLL) acts either as a 1X clock multiplier or a 1/2X clock

multiplier depending on the state of the input control pins T0

and T1. With metal mask options, any type of ratio between

the input clock and output clock can be achieved, including

2X.

Functionality

The PLL maintains the phase and frequency relationship be-

tween the input clock and the outputs by externally feeding

back FBOUT to FBIN. Any change in the input will be tracked

by all 10 outputs. However, the change at the outputs will

happen smoothly so no glitches will be present on any driven

input. The PLL circuitry matches rising edges of the input

clock and the output clock. Since the input to FBIN skew is

guaran-teed to ±500ps, the part acts as a “zero delay” buffer.

FS1

FS0

DESCRIPTION

Power-down

Test Mode (PLL Off CLK=outputs)

Normal (PLL On)

Divide by 2 Mode

The ICS9176-01 has a total of eleven outputs. Of these,

FBOUT is dedicated as the feedback into the PLL and another,

Q/2, has an output frequency half that of the remaining nine.

These nine outputs can either be running at the same speed as

the input, or at half the frequency of the input. With Q/2 as the

feedback to FBIN, the nine ‘Q’ outputs will be running at twice

the input frequency in the normal divide-by-1 mode. In this

case, the output can go to 120 MHz with a 60 MHz input clock.

The maximum rise and fall time of an output is 1ns and each is

TTL-compatible with a 40mA symmetric drive.

Block Diagram

TheICS9176-01is fabricated using CMOS technology which

results in much lower power consumption and cost compared

with the gallium arsenide based 1086E. The typical operating

current for the ICS9176-01 is 60mA versus 115mA for the

GA1086E.

Pentium is a trademark of Intel Corporation.

ICS9176-01-01RevB061297P

ICS reserves the right to make changes in the device data identified in this publication

without further notice. ICS advises its customers to obtain the latest version of all

device data to verify that any information being relied upon by the customer is current

and accurate.

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与9176Q-01相关器件

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91770-322	AMPHENOL	获取价格	Board Connector, 22 Contact(s), 2 Row(s), Female, Straight, Surface Mount Terminal,
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917704-1	MACOM	获取价格	AMP Soft Shell Pin and Socket Connectors
917705-1	MACOM	获取价格	AMP Soft Shell Pin and Socket Connectors

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