Datasheet > 9148F-18

9148F-18

更新时间： 2024-01-07 00:12:18

品牌	Logo	应用领域
艾迪悌 - IDT		时钟光电二极管外围集成电路晶体
页数	文件大小	规格书
12页	285K
描述
Processor Specific Clock Generator, 100MHz, CMOS, PDSO28, 0.209 INCH, SSOP-28

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9148F-18 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	SSOP	包装说明：	0.209 INCH, SSOP-28
针数：	28	Reach Compliance Code：	unknown
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.73	JESD-30 代码：	R-PDSO-G28
JESD-609代码：	e3	长度：	10.2 mm
湿度敏感等级：	1	端子数量：	28
最高工作温度：	70 °C	最低工作温度：
最大输出时钟频率：	100 MHz	封装主体材料：	PLASTIC/EPOXY
封装代码：	SSOP	封装等效代码：	SSOP28,.3
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, SHRINK PITCH
峰值回流温度（摄氏度）：	260	电源：	2.5/3.3,3.3 V
主时钟/晶体标称频率：	14.318 MHz	认证状态：	Not Qualified
座面最大高度：	2 mm	子类别：	Clock Generators
最大压摆率：	100 mA	最大供电电压：	3.465 V
最小供电电压：	3.135 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Matte Tin (Sn) - annealed
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	30
宽度：	5.3 mm	uPs/uCs/外围集成电路类型：	CLOCK GENERATOR, PROCESSOR SPECIFIC
Base Number Matches：	1

9148F-18 数据手册

Integrated

Circuit

Systems, Inc.

ICS9148-18

Pentium/Pro System Clock Chip

General Description

The ICS9148-18 is a Clock Synthesizer chip for Pentium and

PentiumPro CPU based Desktop/Notebook systems that will

provide all necessary clock timing.

Features

•

Generates system clocks for CPU, PCI,

plus14.314MHzREF0.

•

Supports single or dual processor systems

Skew from CPU (earlier) to PCI clock (rising edges for

100/33.3MHz)1to4ns

Features include two CPU and six PCI clocks. One reference

output is available equal to the crystal frequency.Additionally,

the device meets the Pentium power-up stabilization

requirement, acheiving stable CPU and PCI clocks 2ms after

power-up.

•

Separate 2.5V and 3.3V supply pins

2.5Vor3.3Voutput:CPU

3.3Voutputs:PCI, REF

No power supply sequence requirements

Uses external 14.318MHz crystal, no external load cap

required for C_L=18pF crystal

PD# pin can enable a low power mode by stopping crystal

OSC and PLL stages. Other power management features

include, CPU_STOP# which stops CPU (0:1) clocks, and

PCI_STOP#whichstopsPCICLK(0:4)clocks.

•

28 pin209milSSOP

High drive CPUCLK outputs typically provide greater than 1

V/ns slew rate into 20pF loads. PCICLK outputs typically

provide better than 1V/ns slew rate into 30pF loads while

maintaining 50 5%dutycycle. TheREFclockoutputtypically

provides better than 0.5V/ns slew rates.

Pin Configuration

The ICS9148-18 accepts a 14.318MHz reference crystal or

clock as its input and runs on a 3.3V core supply.

Block Diagram

28 pin SSOP

Power Groups

VDD = Supply for PLL core

VDD1=REF0,X1,X2

VDD2=PCICLK_F,PCICLK(0:4)

VDDL=CPUCLK(0:1)

Ground Groups

GND=GroundSourceCore

GND1=REF0,X1,X2

GND2=PCICLK_F,PCICLK(0:4)

GNDL=CPUCLK(0:1)

Pentium is a trademark on Intel Corporation.

9148-18RevC12/02/05

ICS reserves the right to make changes in the device data identified in this

publication without further notice. ICS advises its customers to obtain the latest

version of all device data to verify that any information being relied upon by the

customer is current and accurate.

12 3 4 5 6 7...12

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