Datasheet > 8V19N850

8V19N850

更新时间： 2023-12-20 18:44:47

品牌	Logo	应用领域
瑞萨 - RENESAS		/
页数	文件大小	规格书
177页	3221K
描述
Radio Synchronizer

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8V19N850 数据手册

8V19N850 Datasheet

Features (Full List)

▪ High-performance radio clock synchronizer clock

▪ Device clock domain (RF-PLL) with support for JESD204B/C

▪ Digital clock domain (Ethernet, FEC) with support for eEEC and T-BC/T-TSC Class C

▪ Dual DPLL front-end with independent clock paths

▪ Compliant to ITU-T G.8262 (EEC1/2), G.8262.1 (eEEC), and G.8273.2 (T-BC/T-TSC)

▪ External control of the DCO for IEEE1588 (with a resolution of 1.1 × 10^-7ppb)

▪ Reference monitors for input LOS, activity and frequency

▪ Fast lock to input signals, incl. 1PPS lock

▪ Digital holdover with a 1.1 × 10^-7ppb accuracy

▪ Programmable DPLL loop bandwidth 1mHz - 6kHz

▪ Configurable phase delay (range: 1UI)

▪ Hitless input switching with < 1ns output phase error

▪ 2 differential clock reference inputs

▪ LVDS and LVPECL compatible, non-inverted input also supports LVCMOS

▪ 1PPS (1Hz) to 1GHz input frequency

▪ 1 external synchronization input for JESD204B/C (LVCMOS)

▪ 16 differential outputs

▪ 12 device clock domain outputs (from RF-PLL), 6 clock and 6 SYSREF outputs

▪ 4 digital clock domain outputs

▪ Low-power LVPECL/LVDS outputs support configurable signal amplitude, DC and AC coupling and LVPECL, LVDS line terminations

techniques

▪ Device clock outputs programmable in output amplitude

▪ Frequency range: 0.4608MHz–2.94912GHz (RF-PLL) and up to 1GHz (Digital clocks)

▪ 1PPS (Digital clocks) for T-BC/T-TSC

▪ Dedicated phase management capabilities

▪ Static phase delay for every device clock and SYSREF output

▪ Static and dynamically adjustable phase delay in each DPLL

▪ Supports less than ±0.5ns input to output phase offset

▪ Optimized for low phase noise

▪ Device clocks (RF-PLL): -149.9dBc/Hz (1MHz offset; 245.76MHz clock)

▪ Serial interface ports

▪ 3/4-wire SPI or 2-wire I3C (including legacy I²C), pin-mapped, for phase/frequency control and other configurations

▪ Single I²C master boot for obtaining a start-up configuration

▪ Serial control I/O voltage: 1.8V (outputs: selectable 1.8/3.3V voltage)

▪ Supply voltage (core): 3.3V; (outputs): 3.3V, 2.5V, and 1.8V

▪ Package: 10 × 10 mm 88-VFQFPN

▪ Board temperature range: -40°C to +105°C

December 4, 2023

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