5秒后页面跳转
8N4S270AC-1080CDI PDF预览

8N4S270AC-1080CDI

更新时间: 2024-01-13 04:02:35
品牌 Logo 应用领域
艾迪悌 - IDT 机械输出元件振荡器
页数 文件大小 规格书
18页 606K
描述
LVDS Output Clock Oscillator

8N4S270AC-1080CDI 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:ActiveReach Compliance Code:compliant
风险等级:5.71其他特性:ENABLE/DISABLE FUNCTION; DIFFERENTIAL OUTPUT; TRAY
最长下降时间:0.45 ns频率调整-机械:NO
频率稳定性:100%JESD-609代码:e3
安装特点:SURFACE MOUNT标称工作频率:125 MHz
最高工作温度:85 °C最低工作温度:-40 °C
振荡器类型:LVDS物理尺寸:7.0mm x 5.0mm x 1.55mm
最长上升时间:0.45 ns最大供电电压:3.465 V
最小供电电压:3.135 V标称供电电压:3.3 V
表面贴装:YES最大对称度:53/47 %
端子面层:Matte Tin (Sn)Base Number Matches:1

8N4S270AC-1080CDI 数据手册

 浏览型号8N4S270AC-1080CDI的Datasheet PDF文件第4页浏览型号8N4S270AC-1080CDI的Datasheet PDF文件第5页浏览型号8N4S270AC-1080CDI的Datasheet PDF文件第6页浏览型号8N4S270AC-1080CDI的Datasheet PDF文件第8页浏览型号8N4S270AC-1080CDI的Datasheet PDF文件第9页浏览型号8N4S270AC-1080CDI的Datasheet PDF文件第10页 
IDT8N4S270 Data Sheet  
LVDS FREQUENCY-PROGRAMMABLE CRYSTAL OSCILLATOR  
Table 5. AC Characteristics, VDD = 3.3V 5% or 2.5V 5%, TA = -40°C to 85°C  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
Single-side band phase noise,   
10MHz from Carrier  
N(10M)  
231.25MHz  
-141  
dBc/Hz  
tR / tF  
odc  
Output Rise/Fall Time  
Output Duty Cycle  
20% to 80%  
50  
47  
450  
53  
ps  
%
Device Startup Time After  
Power Up  
tSTARTUP  
20  
ms  
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is  
mounted in a test socket with maintained transverse airflow greater than 500lfpm. The device will meet specifications after thermal equilibrium  
has been reached under these conditions.  
NOTE: XTAL parameters (initial accuracy, temperature stability, aging and total stability) are guaranteed by manufacturing.  
NOTE 1: This parameter is defined in accordance with JEDEC standard 65.  
NOTE 2: Please refer to the phase noise plot.  
NOTE 3: Please see the FemtoClock NG Ceramic 5x7 Modules Programming guide for more information on PLL feedback modes and the  
optimum configuration for phase noise. Integer PLL feedback is the default operation for the dddd = 1xxx order codes.  
IDT8N4S270CCD REVISION A AUGUST 31, 2012  
7
©2012 Integrated Device Technology, Inc.  

与8N4S270AC-1080CDI相关器件

型号 品牌 描述 获取价格 数据表
8N4S270AC-1086CD IDT LVDS Output Clock Oscillator

获取价格

8N4S270AC-1086CD8 IDT LVDS Output Clock Oscillator

获取价格

8N4S270AC-1086CDI IDT LVDS Output Clock Oscillator

获取价格

8N4S270AC-1088CDI IDT LVDS Output Clock Oscillator

获取价格

8N4S270AC-1095CDI IDT LVDS Output Clock Oscillator

获取价格

8N4S270AC-1095CDI8 IDT LVDS Output Clock Oscillator

获取价格